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13-1 introduction preliminary programmable peripheral psd7xx family field-programmable microcontroller peripherals with supervisory functions key features o a simple, programmable interface to 8 or 16 bit microcontrollers using either multiplexed or non-multiplexed busses. the bus interface logic directly decodes microcontroller control signals. microcontroller families supported include the intel 8031, 80196, 80186, 80c251 and 80386ex; motorola 68hc11, 68hc16, 68hc12 and 683xx; philips 8031 and 8051xa; national 16000; zilog z80 and z8; and neuron 3150. o three plds with 12 output micro ? cells and 24 input micro ? cells, 66 inputs and 132 product terms. the psd7xx plds may be used to efficiently implement a variety of logic functions including state machines and address decoders for internal and external control. the pld also provides seven external chip select outputs and generates control for the watchdog timer. o embedded input and output micro ? cells enable efficient implementation of user defined system logic functions that require both microcontroller software and hardware interaction. the psd7xx series is the first family of psd field programmable microcontroller peripherals that includes supervisory control functions. psd7xx devices are used to rapidly implement a highly integrated embedded control system. psd7xx devices integrate many of the peripheral functions inherent in microcontroller based applications including: eprom, sram, programmable logic, reconfigurable i/o ports, programmable power management, voltage monitor, and watchdog timer. the psd7xx family provides a complete solution for microcontroller support and protection. the psd7xx family is developed around an innovative ?icrocontroller-macrocell?logic architecture called the micro ? cell. the micro ? cell was specifically created to address the unique requirements of embedded system designs. it allows direct connection between the system address/data bus and the psd registers which greatly simplifies communication between the mcu and supporting devices. in addition to the micro ? cell based pld, the psd7xx offers all of the supervisory functions needed to monitor embedded system performance. these functions include programmable voltage monitor, watchdog timer, reset pulse generator and an automatic battery backup of the on-board sram. since the supervisory functions are fully programmable, the psd7xx offers the flexibility of using a standard, off the shelf product in a variety of designs under different voltage, reset and clock frequency requirements.
psd7xx family 13-2 o the psd7xx pro vides all the super visor y functions required f or a microcontroller based system. the super visor y f eatures include: system po w er supply monitor ing with configur ab le tr ip points . user prog r ammab le w atchdog timer , controlled b y ppld product ter ms . reset gener ation based on input from: 1. v oltage compar ator with prog r ammab le inter nal or e xter nal tr ip point. 2. push b utton or system reset input. 3. w atchdog timer time out. a utomatic batter y-bac kup of inter nal sram wr ite protect of inter nal sram and e xter nal batter y bac k up de vice . reset input debounce filter . prog r ammab le reset pulse width gener ator . o p o w er management unit reduces the de vice standb y current to 25 a typical. o t w enty se v en individually configur ab le i/o p or t pins . the p or ts ma y be used as mcu i/os , pld i/os , latched mcu address outputs or special function i/os . sixteen i/o por t pins can be configured as open dr ain outputs . o inter nal epr om in densities of 256 kbit, 512 kbit and 1 mbit, configur ab le in eight or sixteen-bit widths . the epr om is divided into eight equal-siz e b loc ks , accessib le b y user-specified addresses . the access time includes address latching and pld decoding. the epr om includes a lo w po w er option. o inter nal 4 kbit sram can be configured in eight or sixteen-bit data widths . the sram retains data if po w er is lost b y automatically s witching to standb y po w er . o a page register e xpands the microcontroller address space b y a f actor of sixteen. o a secur ity bit pre v ents cop ying the psd7xx configur ation and pld logic as w ell as the epr om contents on de vice prog r ammers . o the prog r ammab le p o w er management unit (pmu) suppor ts tw o separ ate , lo w-po w er modes allo wing oper ations with as little as 25 a (at 5v v cc ). the de vice can automatically detect a lac k of microcontroller activity and put the psd into po w er do wn mode . o the de vices are a v ailab le in epr om v ersions . the cer amic pac kage is ideal f or prototyping and lo w-v olume production, and in o tp v ersions f or high-v olume , lo w-cost applications . o p ac kage choices include 52 pin plastic (j) and cer amic (l) chip carr iers . o psd7xx f amily de v elopment is suppor ted b y the wsi pc based psdsof t design system. the softw are is ms-windo ws and windo ws 95 compatib le . the suite includes psdabe l (abel ), to specify the pld logic , and an efficient fitter . the tool also includes the psdsilosiii sim ulator from simucad . the magicpro iii prog r ammer is an engineer ing de v elopment tool and can prog r am an y psd de vice . key featur es (cont.) please ref er to the re vision b loc k at the end of this document f or updated inf or mation.
psd7xx family 13-3 page reg pmu including cmiser features vstdby i/o port programmable i/o port programmable i/o port programmable i/o port programmable mcu address/data ad0 -ad15 mcu control interface control rd, wr security feature clkin 46 24 66 66 greset or ereset pld input bus pld input bus output micro ? cell feedback input micro ? cell & input ports direct micro ? cell output to data bus eprom sram eight blocks 256 k ? mbit eprom 4k bits battery back - up battery back-up i/o decode external cs pld decode pld mcu address / 8 or 16-bit data / control bus 7 external chip selects peripheral selects general pld peripheral pld chip select to i/o allocator pt alloc. micro ? cell allocator direct micro ? cells access from data bus 104 pt 2 pt 6 nibble pt i/o ports pa0 pa7 pb0 pb7 pd0 pd2 pc0 pc1 pc3 pc7 12 output micro ? cells watchdog timer power monitor reset pulse generator 24 input micro ? cells (port a,b,c) (pc2) reset vtp rst out wdog on superv clk ce out vstby on psd7xx architectural overview (cont.) figure 1. psd7xx block diagram
psd7xx family 13-4 general infor mation development system the psd7xx f amily of field prog r ammab le microcontroller p er ipher als combines super visor y control functions , memor y , pld and inno v ativ e system architecture to pro vide a user-prog r ammab le , f eature r ich, lo w-po w er solution to microcontroller system design. the user prog r ammab le super visor y functions integ r ated inside the psd7xx protect embedded systems from f ailure due to sudden loss of po w er , po w er supply glitches , signal corr uption, and memor y loss . the high le v el of integ r ation of the psd7xx de vice dr amatically reduces the n umber of discrete components g reatly simplifying embedded system de v elopment. the psd7xx f amily is suppor ted b y the windo ws-based psdsoft de v elopment system. the psdsoft design flo w is sho wn in figure 2. the pld design entr y is done using psdabel, which creates a minimiz ed logic implementation, and pro vides logic sim ulation of the plds . the psd7xx bus interf ace , i/o p or t configur ation, and super visor y function settings are entered in psdconfigur ation. the psdcompiler , compr ised of a fitter and an address tr anslator , gener ates an object file from the psdabel, psdconfigur ation and mcu code files . the object file is then do wnloaded to a prog r ammer (magicpro iii, data i/o , or other third par ty prog r ammer f or de vice prog r amming) or to the psdsim ulator (psdsilos iii logic sim ulator) f or de vice-le v el sim ulation. psdabel psdcompiler psdsimulator psdprogrammer pld description .obj file configure psd bus interface generate abel file or use design template fitter pld fitting psdsilos iii chip simulation magic pro iii programmer chip programming address translator eprom mapping psdconfiguration third party programmers program code file figur e 2. psdsoft development t ools
psd7xx family device v ersions 13-5 psd7xx family t able 1. psd7xx pr oduct matrix par t bus i/o eprom sram # w idth pins k bit k bit psd701s5 x8/x16 27 256 4 psd711s5 x8 27 256 4 PSD702S5 x8/x16 27 512 4 psd712s5 x8 27 512 4 psd703s5 x8/x16 27 1024 4 psd713s5 x8 27 1024 4 there are 6 de vices in the psd7xx f amily . the par t classifications are based on epr om siz e and data b us width. the f eatures of each par t are listed in t ab le 1. the psd7xx windo w pac kage v ersions are ideal f or gener al pur pose embedded systems de v elopment. the psd7xx o tp v ersions deliv er the lo w est cost psd7xx solution.
psd7xx family 13-6 the f ollo wing tab le descr ibes the pin names and pin functions of the psd7xx. pins that ha v e m ultiple names and/or functions are defined b y configur ation. t able 2. psd7xx pin descriptions pin name pin t ype function description adio 0 ? 3 0 37 i/o address/data p or t, interf ace to microcontroller bus 1. input pins f or m ultiple x ed lo w order address/data b yte . ale or as latches address a0-7. the psd dr iv es data out only if read is activ e and one of the inter nal psd functional b loc ks is selected. 2. address a0-7 inputs f or non-m ultiple x ed b us or 80c251 mode 3. a4/d0-a11/d7 inputs in 80c51xa mode 4. address (or latched address) inputs to pld adio 8 ?5 3 9 46 i/o address/data p or t, interf ace to microcontroller bus 1. address a8-15 inputs in 8-bit data b us mode , or as m ultiple x ed high order address/data b yte inputs in 16-bit data b us mode . ale or as latches address a8-15. the psd dr iv es data out only if read is activ e and one of the inter nal psd functional b loc ks is selected. 2. address a8-15 inputs in non-m ultiple x ed b us mode 3. ad8-ad15 inputs in 80c251 mode 4. a12-a19 or a12/d8 - a19/d15 inputs in 80c51xa mode 5. address (or latched address) inputs to pld cntl0) 47 i wr ite input pin with m ultiple configur ations . depending on the mcu interf ace selected, this pin can be: (wr, 1. wr ?activ e lo w wr ite input r_w , 2. r_w ?read/wr ite pin, lo w f or wr ite b us cycle wrl) 3. wrl ?f or 16 bit data b us only , wr ite to lo w b yte , activ e lo w 4. control signal (cntl0) input to pld cntl1 50 i read or data strobe input pin with m ultiple configur ations . depending on the mcu interf ace selected, this pin can be: (rd , 1. rd ?activ e lo w read input e, 2. e ?e cloc k input. ds , dur ing a wr ite b us cycle , e is high and r/w is lo w lds , dur ing a read b us cycle , e is high and r/w is high psen) 3. ds ?data strobe , activ e lo w 4. lds ?strobe f or lo w data b yte , 16-bit data b us mode , activ e lo w 5. psen ?prog r am select enab le , activ e lo w in read b us cycle (80c251 configur ation) 6. control signal (cntl1) input to pld cntl2 49 i read or other control input pin with m ultiple configur ations . depending on the mcu interf ace selected, this pin can be: (psen, 1. psen ?prog r am select enab le , activ e lo w in code f etch bhe, b us cycle uds , 2. bhe ?high b yte enab le , 16-bit data b us siz0) 3. uds ?strobe f or high data b yte , 16-bit data b us mode , activ e lo w 4. siz0 ?byte enab le input 5. control signal (cntl2) input or gener al input to pld
psd7xx family 13-7 pin name pin t ype function description reset 48 i activ e lo w input. resets i/o p or ts , pld micro ? cells and some of the configur ation registers . must be activ e at po w er up . p a0 29 i/o p or t a, p a0 ?3. this por t is pin configur ab le and has p a1 28 m ultiple functions: p a2 27 1. mcu i/o ?standard output or input por t p a3 25 2. exter nal chip select (ecspld) output, or input to gpld 3. latched address outputs (see t ab le 4) 4. as address a0-3 inputs in 80c51xa mode 5. as data bus p or t (d 0 3) in non-m ultiple x ed b us configur ation 6. p er ipher al i/o mode p a4 24 i/o p or t a, p a 4 7 . this por t is pin configur ab le and has p a5 23 cmos m ultiple functions: p a6 22 or 1. mcu i/o ?standard output or input por t p a7 21 open 2. gpld micro ? cell (mcellab) output or input dr ain 3. latched address outputs (see t ab le 4) 4. as data bus p or t (d 4 7) in non-m ultiple x ed b us configur ation 5. p er ipher al i/o mode pb0 7 i/o p or t b , pb 0 3. this por t is pin configur ab le and has pb1 6 m ultiple functions: pb2 5 1. mcu i/o ?standard output or input por t pb3 4 2. exter nal chip select (ecspld) output, or input to gpld 3. latched address outputs (see t ab le 4) 4. as data bus p or t (d8-11) in non-m ultiple x ed b us configur ation with 16-bit data b us pb4 3 i/o p or t b , pb 4 7. this por t is pin configur ab le and has m ultiple pb5 2 cmos functions: pb6 52 or 1. mcu i/o ?standard output or input por t pb7 51 open 2. gpld micro ? cell (mcellab) output or input dr ain 3. latched address outputs (see t ab le 4) 4. as data bus p or t (d1 2 15) in non-m ultiple x ed b us configur ation with 16-bit data b us pc0 20 i/o this por t is pin configur ab le and has m ultiple pc1 19 functions: pc2 18 1. mcu i/o ?standard output or input por t pc3 17 cmos 2. gpld micro ? cell (mcellc) output or input pc4 14 or 3. pc7 pin only ?wr ite strobe (wrh) input f or high b yte . pc5 13 open activ e lo w f or 16-bit mcu with wrh pc6 12 dr ain 4. super visor y function (pin pc1?c6), see t ab le 3. pc7 11 t able 2. psd7xx pin descriptions (cont.)
psd7xx family 13-8 pin name pin t ype function description pd0 10 i/o p or t d pin pd0 can be configured as: (ale) 1. ale input - latches addresses on adio 0 ?5 pins 2. mcu i/o 3. gpld input 4. ecspld output pd1 9 i/o p or t d pin pd1 can be configured as: (clkin) 1. mcu i/o 2. gpld input 3. exter nal chip select (ecspld) output 4. clkin cloc k input ?cloc k input to the gpld micro ? cells , the apd po w er do wn counter and gpld and arr a y pd2 8 i/o p or t d pin pd2 can be configured as: (csi) 1. mcu i/o 2. gpld input 3. exter nal (ecspld) output 4. csi input ?when lo w , the csi enab les the psd epr om/sram. when high, the epr om/sram are disab led to conser v e po w er v cc 15 p o w er pins 38 gnd 1 ground pins 16 26 t able 2. psd7xx pin descriptions (cont.) pin name pin t ype function description pc1 (rst_out) 19 o activ e lo w reset output. pc2 (vstby) 18 i sram standb y v oltage (batter y) input. pc3 (ceout) 17 o chip select output that can be used f or e xter nal non-v olatile wr itab le memor y . this chip select becomes inactiv e automatically when the psd7xx is s witched to standb y v oltage . use to conser v e po w er in e xter nal batter y bac kup sram or pre v ent unw anted wr ites to e xter nal eepr om, sram, or flash. pc4 (vstby on) 14 o pin is dr iv en high when psd7xx is s witched o v er to standb y v oltage . pc5 (rst_out) 13 o activ e high reset output. pc6 (vtp) 12 i exter nal ref erence v oltage input f or the v oltage compar ator . t able 3. psd7xx super visor y i/o pins
psd7xx family 13-9 micr ocontr oller por t a (3:0) por t a (7:4) por t b (3:0) por t b (7:4) 8051xa (8-bit) n/a address [7:4] address [11:8] n/a 80c251 (p age mode) n/a n/a address [11:8] address [15:12] all other 8-bit multiple x ed address [3:0] address [7:4] address [3:0] address [7:4] 8051xa (16-bit) n/a address [7:4] address [11:8] address [15:12] all other 16-bit multiple x ed address [3:0] address [7:4] address [11:8] address [15:12] 8-bit non-multiple x ed n/a n/a address [3:0] address [7:4] bus t able 4. latched addr ess outputs n/a = not applicab le * ref er to the i/o p or t section on ho w to enab le the latched address output function. t ab les 5 and 5a sho w the offset address to the psd7xx registers relativ e to the csiop base address . the csiop space is the 256 b ytes of address that is allocated b y the user to the inter nal psd7xx registers . some motorola 16-bit microcontrollers , including the m68hc16, m68302 and m683xx, ha v e a diff erent data b yte or ientation requir ing separ ate address offset maps . t ab le 5 sho ws the csiop address offsets f or all mcus e xcept those from motorola in 16-bit mode . t ab le 5a sho ws the address offsets f or motorola mcus in 16-bit mode . i/o por t latched addr ess output assignments* psd7xx register description and addr ess of fset
psd7xx family 13-10 psd7xx register description and addr ess of fset ( cont.) register name por t a por t b por t c por t d othe r * description data in 00 01 10 11 reads p or t pin as input, mcu i/o input mode control 02 03 selects mode betw een mcu i/o or address out data out 04 05 12 13 stores data f or output to p or t pins , mcu i/o output mode direction 06 07 14 15 configures p or t pin as input or output dr iv e 08 09 16 17 configures p or t pin betw een cmos , open dr ain and sle w rate input micro ? cell 0a 0b 18 reads input micro ? cell enab le out 0c 0d 1a reads the status of the output enab le to the i/o p or t dr iv er output 20 20 21 read ? reads output of micro ? cell micro ? cells (mcellc , mcellab) wr ite ? loads micro ? cell flip-flops pmmr0 b0 p o w er management register 0 pmmr1 b2 p o w er management register 1 p age e0 p age register vm e2 8031/pio configur ation register status d8 read only super visor y register . indicates the status and source of reset and ref erence v oltage le v el. reset-clr d6 wr ite only . a wr ite to the register clears the reset status bits in the status register . supv-pins d a read only . indicates the status of all super visor y i/o pins . wd-conf d4 read only . indicates the configur ation of the w atchdog timer . wd-count d0 contains w atchdog timer count bits 0 7. wd-misc d2 contains w atchdog timer count bit 8, the cloc k source and reset pulse width. t able 5. register addr ess of fset * other registers that are not par t of the i/o por ts .
psd7xx family 13-11 register name por t por t por t por t othe r * description a b c d data in 01 00 11 10 reads p or t pin as input, mcu i/o input mode control 03 02 selects mode betw een mcu i/o or address out data out 05 04 13 12 stores data f or output to p or t pins , mcu i/o output mode direction 07 06 15 14 configures p or t pin as input or output dr iv e 09 08 17 16 configures p or t pin betw een cmos , open dr ain and sle w r ate input micro ? cell 0b 0a 19 reads input micro ? cell enab le out 0d 0c 1b reads the status of the output enab le to the i/o p or t dr iv er output micro ? cell 21 21 20 read ? reads output of micro ? cells (mcellc , mcellab) wr ite ? loads micro ? cell flip-flops pmmr0 b1 p o w er management register 0 pmmr1 b3 p o w er management register 1 p age e1 p age register vm e3 8031/pio configur ation register status d9 read only super visor y register . indicates the status and source of reset and ref erence v oltage le v el. reset-clr d7 wr ite only . a wr ite to the register clears the reset status bits in the status register . supv-pins db read only . indicates the status of all super visor y i/o pins . wd-conf d5 read only . indicates the configur ation of the w atchdog timer . wd-count d1 contains w atchdog timer count bits 0 7. wd-misc d3 contains w atchdog timer count bit 8, the cloc k source and reset pulse width. t able 5a. register addr ess of fset for 16-bit motor ola micr ocontr ollers in 16-bit mode psd7xx register description and addr ess of fset (cont.) * other registers that are not par t of the i/o por ts .
psd7xx family 13-12 psd7xx de vices consist of se v er al major functional b loc ks . figure 1 sho ws the architecture of the psd7xx f amily . the functions of each b loc k are descr ibed br iefly in the f ollo wing sections . man y of the b loc ks perf or m m ultiple functions , and are user configur ab le . plds the de vice contains f our pld b loc ks each optimiz ed f or a diff erent function as sho wn in t ab le 6. the functional par titioning of the plds reduces po w er consumption, optimiz es cost/perf or mance and ease of design entr y . the decode pld (dpld) is used to decode and gener ate chip selects f or the psd7xx inter nal memor y , registers and per ipher al mode . the exter nal chip select pld (ecspld) is optimiz ed to gener ate chip selects f or de vices e xter nal to the psd7xx. the gener al pur pose pld (gpld) can implement user defined logic functions . the dpld and ecspld ha v e combinator ial outputs while the gpld has 12 output micro ? cells . the psd7xx also has 24 input micro ? cells that can be configured as inputs to the pld . the plds receiv e their inputs from the pld input b us and are diff erentiated b y their output destinations , n umber of product ter ms , and micro ? cells . the p er ipher al pld (ppld) is dedicated to gener ate control signals f or the w atchdog timer . psd7xx ar chitectural over view name abbr eviation inputs outputs pr oduct t er ms decode pld dpld 46 12 13 exter nal chip select pld ecspld 24 7 7 gener al pld gpld 66 12 110 p er ipher al pld ppld 66 2 2 t able 6. i/o por ts the psd7xx has 27 i/o pins divided among f our por ts . each i/o pin can be individually configured to pro vide man y functions . p or ts a, b , c and d can be configured as standard mcu i/o por ts , pld i/o , or latched address outputs f or microcontrollers using m ultiple x ed address/data b usses . p or ts a and b can also be configured as a data por t f or microcontrollers with a non-m ultiple x ed b us . in these modes , p or t a is connected to d 0 ? and p or t b to d 8 ?5. super visor y functions the psd7xx pro vides all the super visor y functions required f or an embedded system. a v oltage compar ator monitors the system po w er supply and gener ates a reset if v cc drops belo w inter nal or e xter nal ref erence v oltages (h yster isis included). the polar ity and dur ation of the reset output signal is prog r ammab le . a noise filter f or the reset input is pro vided to debounce the source (pushb utton or other). the inter nal psd7xx sram is automatically s witched to standb y v oltage if v cc drops belo w the standb y v oltage v alue . when s witcho v er occurs , the inter nal sram is wr ite protected and a single user defined chip select output immediately goes inactiv e . this special chip select suppor ts the use of an additional e xter nal batter y bac kup sram (to ensure lo w po w er consumption dur ing a f ault) or pro vides protection against inadv er tent wr ites to e xter nal flash or eepr om. a w atchdog timer is pro vided to monitor softw are integ r ity . nor mal prog r am flo w will contin ually reset the w atchdog timer . ho w e v er , if prog r am flo w malfunctions and hangs up , the timer will timeout and reset the system. this 9-bit w atchdog timer is prog r ammab le and can supply its o wn independent cloc k source .
psd7xx family 13-13 psd7xx ar chitectural over view (cont.) micr ocontr oller bus inter face the psd7xx easily interf aces with most popular eight and sixteen-bit microcontrollers with either m ultiple x ed or non-m ultiple x ed address/data b usses . the de vice is configured to respond to the microcontroller control signals which are also used as inputs to the plds . memor y the psd7xx contains epr om and sram. the epr om densities a v ailab le are 256 kbit, 512 kbit and 1 mbit. the memor y space is divided into eight equally-siz ed b loc ks . each b loc k can be located in a diff erent address space defined b y the user . the access time of the epr om includes the address latching and dpld decoding. the 4 kbit sram ma y be used as a scr atch pad memor y and an e xtension of the microcontroller sram. the sram data is retained in the e v ent of a system po w er do wn, pro vided a bac kup batter y is connected to the vstb y pin (pc2). switching from the v cc supply to standb y po w er occurs automatically when v cc drops belo w vstb y v oltage . page register the f our-bit p age register e xpands the address r ange of the microcontroller b y sixteen times . the paged address can be used as par t of the address space to access e xter nal memor y and per ipher als or inter nal epr om, sram and i/o . power management unit the p o w er management unit (pmu) in the psd7xx enab les the user to control the po w er consumption on selected functional b loc ks based on system requirements . the pmu includes an a utomatic p o w er do wn unit (apd) that will tur n off de vice functions due to microcontroller inactivity in one of tw o modes: the p o w er do wn mode and sleep mode . other po w er sa ving f eatures , such as the cmiser in the pmu , allo w the epr om/sram to oper ate at a slo w er r ate to conser v e po w er .
psd7xx family 13-14 the psd7xx functional blocks the psd7xx consists of fiv e major functional b loc ks: o pld block o bus inter face o i/o por ts o memor y block o power management unit o super visor y function the functions of each b loc k are descr ibed in the f ollo wing sections . man y of the b loc ks perf or m m ultiple functions , and are user configur ab le . plds the plds br ing prog r ammab le logic functionality to the psd7xx. after specifying the logic f or the plds b y using the psdabel tool in psdsoft, the logic configur ation is prog r ammed into the de vice and a v ailab le when po w er is applied. the plds (dpld , ecspld , gpld , and ppld) consist of an and arr a y . the gpld architecture includes 12 output micro ? cells in addition to the and arr a y . there are 24 input micro ? cells that can be configured as inputs to the pld . figure 3 sho ws the orga - nization of the pld . the and arr a y is used to f or m product ter ms specified using the psdabel tool in the psdsoft de v elopment system. when the inputs used in a ter m are tr ue , the output is activ e . the gpld input bus consists of 66 signals as sho wn in t ab le 7. both the tr ue and complement v alue of inputs are a v ailab le to the and arr a y . the dpld and ecspld input busses consists of f e w er inputs and is a subset of the 66 inputs . input sour ce input name number of signals mcu address bus a [15:0 ] * 16 mcu control signals cnt l [2:0] 3 p o w er do wn pdn 1 i/o p or ts inputs (input micro ? cells) p a [7:0], p b [7:0], p c [7:0] 24 p or t d inputs p d [2:0] 3 p age register pg r [3:0] 4 p or t a or b micro ? cell f eedbac k mcellab .f b [7: 4 ] 4 p or t c micro ? cell f eedbac k mcellc .f b [7:0] 8 super visor y function wdog_on 1 w atchdog time out super visor y function greset or ereset 1 global reset or expanded reset super visor y cloc k super v_clk 1 2khz inter nal oscillator or clkin/8192 t able 7. gpld inputs * no te: the address inputs are a[19:4] in 80c51xa mode .
psd7xx family 13-15 pld input bus 46 8 24 66 output micro ? cell feedback, input micro ? cell & input ports direct micro ? cell output to data bus csiop select sram select external cs pld decode pld 7 external chip selects port a, b or d peripheral selects general pld chip select to i/o allocator pt alloc. micro ? cell allocator direct micro ? cell access from data bus 104 pt 6 nibble pt 24 input micro ? cell (port a,b,c) 12 output micro ? cell i/o ports eprom selects 3 66 port d inputs wdog en wdog on superv clk greset or ereset wdog clr peripheral pld mcell ab to port a or b mcell c to port c plds (cont.) figure 3. pld block diagram
psd7xx family 13-16 each of the three plds has unique char acter istics suited f or its applications . the y are descr ibed in the f ollo wing sections . decode pld the decode pld (dpld), sho wn in figure 4, is used to select the inter nal psd7xx functions: epr om b loc ks , sram, registers (csiop) and the p or t a p er ipher al mode . all the select signals are activ e high and ha v e one product ter m, e xcept es7 which has tw o . the csiop is the select line f or the psd7xx inter nal registers that occupies 256 b ytes of memor y space . a second le v el decoder selects a register based on the address inputs a[7-0]. each epr om b loc k has its o wn chip select. the chip select of the eighth epr om b loc k has tw o product ter ms , es7a and es7b . this allo ws the eighth b loc k to reside in tw o memor y spaces , where es7b can typically select reset v ectors or configur ation b ytes that are stored in the mcu address space . psel 0 & 1 are used as inputs to p or t a to control the por t s p er ipher al i/o mode oper ation. usually psel 0&1 are defined in ter m of the mcu address inputs . this mode is e xplained in the i/o p or t section. plds (cont.) input sour ce input name number of bits mcu address bus a [15: 0 ] * 16 i/o p or ts p a [7 : 0 ], p b [ 7: 0 ], 24 p or t a, b , c p c [7 : 0] p age register pg r [3 : 0 ] 4 control signal cntl1 (read) 1 super visor y function greset or ereset 1 super visor y function wdog_on 1 t able 8. dpld inputs * no te: the address inputs are a [19: 4 ] in 80c51xa mode . a[3:0] are assigned to p or t a.
psd7xx family 13-17 (inputs) (24) (4) (16) (1) read cntl1 (1) i /o ports (port a, b, c) pgr0 - pgr3 a [ 15: 0 ] * greset or ereset (1) wdog _ on es0 es1 es2 es3 es4 es5 es6 es7a es7b rs0 csiop psel0 psel1 8 eprom block selects es7 ram select i/o decoder select peripheral mode select figur e 4. dpld logic ar ray plds (cont.) * no te: the address inputs are a [19: 4 ] in 80c51xa mode , a [3:0] are assigned to p or t a.
psd7xx family 13-18 ecspld output por t a, b, or d assignments ecs0 p a0, pb0 ecs1 p a1, pb1 ecs2 p a2, pb2 ecs3 p a3, pb3 ecs4 pd0* ecs5 pd1* ecs6 pd2* t able 10. ecspld output por t assignments the se v en ecspld outputs ma y be dr iv en off the de vice through p or ts a, b , or d , as sho wn in t ab le 10, via the micro ? cell allocator . p or t selection is specified in the psdabel file or assigned b y the psdcompiler . plds (cont.) * p or t d has no output enab le (.oe) product ter ms f or ecs4-6 outputs . exter nal chip select pld the exter nal chip select pld (ecspld) pro vides the means to select e xter nal de vices . the output b uff er of the ecspld can be configured to oper ate in high sle w r ate b y wr iting a ??to the corresponding bit in the dr iv e register . the sle w r ate is a measurement of the r ise and f all times of the output. a higher sle w r ate means a f aster output response while a lo w er sle w r ate is a slo w er response . ref er to t ab le 26 in the i/o section f or setting up the dr iv e register . f aster tr ansitions are more lik ely to cause line reflections and system noise than slo w er r ates . adjusting the sle w r ate allo ws a tr ade-off betw een g reater speed and noise sensitivity . the selection should be based on the perf or mance requirements of the system and its noise char acter istics . set the corresponding bits in the dr iv e register to ??(f or nor mal speed) or ??(f or f ast dr iv e). the def ault v alue is z ero . the ecspld has 24 inputs as sho wn in t ab le 9. its outputs are combinator ial, of either polar ity , and ha v e one product ter m each as sho wn in figure 5. input sour ce input name number of bits mcu address bus a[15:0]* 16 mcu control signals cntl[2:0] 3 p o w er do wn signal pdn** 1 p age register pgr[3:0] 4 t able 9. ecspld inputs * * in 80c51xa mode , the address inputs are a[19:4] ** apd output. when pdn is high, the psd7xx is in po w er do wn mode
psd7xx family 13-19 plds (cont.) (inputs) (4) (16) (3) (1) a [ 15:0 ] pgr [ 3:0 ] cntrl [ 2: 0 ] , read/ write control signals pdn apd output polarity bit polarity bit polarity bit ecs0 ecs1 ecs6 * figur e 5. ecspld logic ar ray general pld the gener al pld (gpld) is used to implement system logic such as mcu loadab le counters , system mailbo x es or handshaking protocols . in addition the gpld can implement r andom logic and state machine functions . the gpld has output and input micro ? cells . the gpld , output and input micro ? cells architectures appear in figure 6 along with the p or t. the micro ? cells are configured using the psdsoft de v elopment system. lik e the other plds , the gpld has an and arr a y which can gener ate up to 110 product ter ms , a maxim um of nine product ter ms f or each of the tw elv e micro ? cells . the input and output micro ? cells are connected to the psd7xx inter nal data b us and can be directly accessed b y the microcontroller . this enab les the mcu softw are to load data into the output micro ? cells or read data from both the input and output micro ? cells . this f eature allo ws efficient implementation of system logic and eliminates the need to connect the data b us to the and logic arr a y as required in most standard pld macrocell architectures . * in 80c51xa mode , these address inputs are a[19:4].
psd7xx family 13-20 i/o ports gpld micro cells input micro cells latched address out mux mux mux mux d d q q q d wr wr pdb product term allocator dir reg select input g/ck product terms from other micro cells polarity select up to 9 product terms clock select pr di ld d/t ck cl q d/t/jk ff select pt clear pt clock global clock pt output enable ( oe ) micro cell feedback i/o port input ale pt input latch gate/clock mcu load pt reset mcu data in comb. reg select micro cell to i/o port allocator gpld output to other i/o ports pld input bus pld input bus mcu address / data / control bus micro cell out to mcu data write control and array gpld output figur e 6. the gpld and i/o por t plds (cont.)
psd7xx family 13-21 output micr o ? cell eight of the output micro ? cells are connected to p or t c pins and are named as mcellc0-7. the remaining f our micro-cells can be connected to p or t a or p or t b and are named as mcellab4-7. if an mcellab output is not assigned to a specific pin in psdabel, the micro ? cell allocator will assign it to either p or t a or b . t ab le 11 sho ws the micro ? cells and p or t assignment. max data bit for data bit for native bor r owed loading or loading or output por t pr oduct pr oduct reading in reading in micr o ? cell assignment t er ms t er ms 8-bit mode 16-bit mode mcellc0 p or t c0 4 5 d0 d8 mcellc1 p or t c1 4 5 d1 d9 mcellc2 p or t c2 4 5 d2 d10 mcellc3 p or t c3 4 5 d3 d11 mcellc4 p or t c4 4 5 d4 d12 mcellc5 p or t c5 4 5 d5 d13 mcellc6 p or t c6 4 5 d6 d14 mcellc7 p or t c7 4 5 d7 d15 mcellab4 p or t a4, b4 3 6 d4 d4 mcellab5 p or t a5, b5 3 6 d5 d5 mcellab6 p or t a6, b6 3 6 d6 d6 mcellab7 p or t a7, b7 3 6 d7 d7 t able 11. output micr o ? cell por t and data bit assignments the pr oduct t er m allocator all micro ? cells ha v e the same basic cell architecture e xcept mcellc has f our nativ e product ter ms and mcellab has three product ter ms . the gpld also has a product t er m allocator with which the psdcompiler can automatically borro w product ter ms from one micro ? cell to another . the mcellc ma y borro w up to fiv e product ter ms from other micro ? cells f or a total of nine product ter ms . the mcellab has three nativ e product ter ms and can borro w up to six product ter ms . borro wing allo ws micro ? cell outputs needing more product ter ms to use the un used product ter ms of others . the architecture of the 12 output micro ? cells , as sho wn in figure 7, consists of nativ e product ter ms and borro w ed product ter ms from other micro ? cells . the polar ity of the product ter m input is controlled b y the xor gate . the micro ? cell can implement either sequential logic , using the flip-flop element, or combinator ial functions . the m ultiple xor selects the combinator ial or the sequential logic as the micro ? cell output. the m ultiple xor output can dr iv e a p or t pin and has also a f eedbac k path to the and arr a y inputs . micr o ? cell flip-flop t ype the flip-flop in the micro ? cell can be configured as a d , t oggle , jk or sr type b y using psdabel in psdsoft. the flip-flop cloc k, preset and clear inputs are dr iv en from a product ter m of the and arr a y . alter nativ ely , the de vice cloc k input (clkin) can be used f or the flip-flop . the preset and clear are activ e high inputs; the flip-flop is cloc k ed b y the r ising edge of the cloc k input. plds (cont.)
psd7xx family 13-22 plds (cont.) pt allocator pt clk pt pt clkin (note 1) feedback ( .fb ) port input and array pld input bus mux mux polarity select ld in clr q pr din comb/reg select port driver input micro cell i/o pin micro cell allocator internal data bus d [ 7:0 ] d [ 15:8 ] ( note 2 ) direction register clear ( .re ) programmable ff ( d / t/jk /sr ) wr enable ( .oe ) preset ( .pr ) rd micro cell cs figur e 7. gpld output micr o ? cell no tes: 1. mcell c has 4 local product ter ms . mcell ab has 3 local product ter ms . max. total product ter ms : 9 2. allocator is f or mcell ab only .
psd7xx family 13-23 loading and reading the micr o ? cells the gpld micro ? cells occup y a memor y location in the mcu address space as defined b y the csiop (ref er to the i/o section). the flip-flops in each of the 12 micro ? cells can be loaded from the data b us b y a microcontroller wr ite b us cycle to the micro ? cell (see i/o p or t section f or micro ? cell addresses). a ??in the data bit that associates with the micro ? cell will load a ??to the flip-flop , a ??in the data bit will load a ??to the flip-flop . the loading b us cycle tak es pr ior ity o v er other flip-flop inputs that include the preset, clear and cloc k. see t ab le 12 f or the data bits that are connected to the micro ? cells . the ability to load the flip-flops and read them bac k is useful in such applications as loadab le counters , shift registers , mailbo x es or handshaking protocols . plds (cont.) ld din clk in pr clr q 1 1 x x x x 1 1 0 x x x x 0 0 x nor mal flip-flop function t able 12. micr o ? cell flip-flop loading no te: ld is ??when the mcu wr ites to the micro ? cell address the output enable the micro ? cell can be connected to a psd7xx i/o pin as pld output. the output enab le of each of the p or t pin output dr iv er is controlled b y a single product ter m (.oe) from the and arr a y ored with the direction register output. upon po w er up , if no output enab le (.oe) equation is defined and the pin is declared as a pld output in psdsoft, the pin is enab led. if the micro ? cell output is declared as inter nal node and not as p or t pin output in the psdabel file , then the p or t pin can be used f or other i/o functions . the inter nal node f eedbac k can be routed as an input to the and arr a y . input micr o ? cell the input micro ? cells as sho wn in figure 8 are used to latch, register or pass incoming p or t signals pr ior to dr iving them onto the pld input b us . the outputs of these micro ? cells can also be read b y the microcontroller through the inter nal data bus . the gpld has 24 input micro ? cells , one f or each pin of p or ts a, b and c . the input micro ? cells are individually configur ab le . the enab le/cloc k f or the latch and flip-flop is dr iv en b y a m ultiple xor whose inputs are a product ter m from the gpld and arr a y and the mcu address strobe (ale). each product ter m output is used to latch/cloc k f our input micro ? cells . p or t inputs [3:0] can be controlled b y one product ter m and [7:4] can be controlled b y another one . the input micro ? cell configur ations are specified b y equations wr itten in psdabel. outputs of the micro ? cells can be read b y the microcontroller via the ?nput micro ? cell b uff er . see the i/o p or t section on ho w to read the micro ? cells . input micro ? cells can use the ale to latch the higher address bits (a31 ?a16). the latched addresses are routed to the pld as inputs . the input micro-cell is par ticular ly useful in handshaking comm unication applications where tw o mcus wish to pass data betw een each other through a commonly accessib le stor age . figure 9 sho ws a typical configur ation where the master mcu wr ites to the p or t a data out register that is read b y the sla v e mcu via the activ ation of the ?la v e-read output enab le product ter m. the sla v e mcu can wr ite to p or t a input micro ? cells b y acti - v ating the sla v e-wr product ter m. the master mcu can then read the input micro ? cells . the sla v e-read and sla v e-wr signals are product ter ms that are der iv ed from the sla v e mcu signals rd , wr, and sla v e_cs .
psd7xx family 13-24 output micro cells c and micro cell ab pt pt feedback and array pld input bus port driver i/o pin internal data bus d [ 7: 0 ] direction register mux mux ale pt q q d d g latch note * input micro cell enable ( .oe ) d ff input micro cell rd figur e 8. input micr o ? cell plds (cont.) * no te: one pt controls 4 input micro ? cells . (input micro ? cells [3:0] or [7:4 ] ).
psd7xx family 13-25 master mcu mcu - rd mcu - rd mcu - wr slave wr slave cs mcu - wr d [ 7:0 ] d [ 7:0 ] gpld d q q d port a data out register port a input micro cell port a slave read slave mcu rd wr psd7xx figur e 9. handshaking communication using input micr o ? cells plds (cont.)
psd7xx family 13-26 plds (cont.) peripheral pld the p er ipher al pld (ppld), sho wn in figure 10, controls the oper ation of the w atchdog timer of the super visor y function. the input to the ppld consists of the same 66 signals that are shared with the gpld (ref er to t ab le 7). the ppld pro vides tw o activ e high outputs , each consists of one product ter m: o wdog_en the w atchdog timer can be enab led either b y the tr ailing edge of the reset gener ated b y the super visor y function, or b y an activ e high wdog_en pulse . the wdog_en product ter m can be defined to become activ e when the microcontroller wr ites to a cer tain address . the wdog_en signal can be activ ated only after the e xter nal reset (ereset) e xpires . o wdog_clr this is an activ e high pulse that re-loads the counter in the w atchdog timer and pre v ents the w atchdog from gener ating a timeout. the wdog_clr product ter m can be defined to become activ e when the microcontroller wr ites to a specific address . greset or ereset pld input bus wdog en wdog on superv clk supervisory function watchdog timer wdog clr figur e 10. ppld logic ar ray
psd7xx family 13-27 bus inter face mcu data bus cntl0 cntl1 cntl2 pc7 pd0** adio0 p a3? a0 8031 8 wr rd psen * ale a0 * 68330 8 r/w ds * * ale a0 * 80198 8 wr rd * * ale a0 * 68hc11 8 r/w e * * as a0 * 80c51xa 8 wr rd psen * ale a4 a 3 a0 80c251 8 wr psen * * ale a0 * 80c251 8 wr rd psen * ale a0 * z8 8 r/w ds * * * a0 * neuron 3150 8 r/w ds * * * a0 * 80196 16 wrl rd bhe * ale a0 * 80196 16 wrl rd * wrh ale a0 * 68hc12*** 16 r/w e a0 * lstrb * 68302 16 r/w lds uds * as * 68330 16 r/w ds bhe * as a0/ble * 68332 16 r/w ds siz0 * as a0 * 80c51xa 16 wrl rd psen wrh ale a4/d0 a3 a1 68lc302 16 wel oe weh as * 80186 16 wr rd bhe * ale a0 * 80c166 16 wr rd bhe * ale a0 * t able 13.micr ocontr oller busses and contr ol signals the ?o-glue logic?psd7xx microcontroller bus interf ace can be directly connected to the most popular microcontrollers . some of these microcontrollers with their b us types and control signals are sho wn in t ab le 13. the interf ace type is specified using the psdsoft tools . ** *not used cntl2 pin can be configured as gpld input. other not used pins (pc7, pd0, p a3-0) can be configured f or other i/o functions . * **ale/as input is optional f or microcontrollers with a non-m ultiple x ed b us . ***this configur ation is f or 68hc12 with non-m ux b us . t ab le 13 sho ws the names of the psd7xx b us interf ace control pins and their functions . the control pins ha v e m ultiple functions and can be configured to interf ace to man y microcontrollers . depending on the microcontroller , some of the control input pins are not required and ma y be used as gpld input or other i/o functions . specific e xamples of interf aces to diff erent microcontrollers are pro vided in the f ollo wing sections . f or microcontrollers that ha v e more than 16 address lines , p or t a, b , or c pins ma y be used as additional address inputs
psd7xx inter face t o a multiplexed bus figure 11 sho ws an e xample of a system using a microcontroller with a m ultiple x ed b us and a psd7xx. the adio por t on the psd7xx is connected directly to the microcontroller address/data b us . the b us ma y be m ultiple x ed only on one b yte (eight-bit data) or on both b ytes (sixteen-bit data). the ale latches the address lines inter nally; latched addresses can be brought out to p or t a or b . the psd7xx dr iv es the adio data b us only when one of its inter nal resources is accessed and the rd input is activ e . psd7xx family 13-28 bus inter face (cont.) micro - controller wr rd bhe ale reset ad [ 7:0 ] ad [ 15:8 ] a [ 15: 8 ] a [ 7: 0 ] or a [ 15:8 ] adio port port a port b port c wr ( cntrl0 ) rd ( cntrl1 ) bhe ( cntrl2 ) rst ale ( pd0 ) port d ( optional ) ( optional ) psd7xx figur e 11. an example of a t ypical multiplexed bus inter face, 8 or 16-bit data bus
psd7xx family 13-29 bus inter face (cont.) micro - controller wr rd bhe ale reset d [ 15: 0 ] a [ 15: 0 ] d [ 15:8 ] a [ 23:16 ] d [ 7:0 ] adio port port a port b port c wr ( cntrl0 ) rd ( cntrl1 ) bhe ( cntrl2 ) rst ale ( pd0 ) port d ( 16-bit data only ) (optional) psd7xx figur e 12. an example of a t ypical non-multiplexed bus inter face, 8 or 16-bit data bus psd7xx inter face t o a non-multiplexed bus figure 12 sho ws an e xample of a system using a microcontroller with a non-m ultiple x ed b us and a psd7xx. the address b us is connected to the adio p or t, and the data b us is connected to p or t a (d[7:0]) and to p or ts b (d[15:8], 16-bit data b us only). the data p or ts are in tr i-state mode when the psd7xx is not accessed b y the microcontroller . should the system address b us e xceed sixteen bits , p or t a, b , or c ma y be used as additional address inputs .
psd7xx family 13-30 bus inter face (cont.) data byte enable refer ence microcontrollers ha v e diff erent data b yte or ientations . the f ollo wing tab les sho w ho w the psd7xx inter prets b yte/w ord oper ation in diff erent wr ite b us configur ations . ev en-b yte ref ers to locations with address a0 equal to z ero and odd b yte as locations with a0 equal to one . bhe a0 d7 ?d0 x 0 ev en byte x 1 odd byte t able 14. 8-bit data bus bhe a0 d15 ?d8 d7 ?d0 0 0 odd byte ev en byte 0 1 odd byte 1 0 ev en byte t able 15. 16-bit data bus w ith bhe wrh wrl d15 ?d8 d7 ?d0 0 0 odd byte ev en byte 0 1 odd byte 1 0 ev en byte t able 16. 16-bit data bus w ith wrh and wrl siz0 a0 d15 ?d8 d7 ?d0 0 0 ev en byte odd byte 1 0 ev en byte 1 1 odd byte t able 17. 16-bit data bus w ith siz0, a0 (motor ola mcu) lds uds d15 ?d8 d7 ?d0 0 0 ev en byte odd byte 1 0 ev en byte 0 1 odd byte t able 18. 16-bit data bus w ith uds, lds (motor ola mcu)
psd7xx family 13-31 micr ocontr oller inter face examples figures 13 through 20 sho w e xamples of the basic connections betw een the psd7xx and some popular microcontrollers . the psd7xx control input pins are labeled as the microcontroller function f or which the y are configured. the mcu interf ace is specified using the psdsoft tools . 80c31 figure 13 sho ws the interf ace to the 80c31 which has an 8-bit m ultiple x ed address/data b us . the lo w er address b yte is m ultiple x ed with the data b us . the microcontroller rd and wr signals ma y be used f or accessing inter nal sram and i/o p or ts while the psen signal is used to read the epr om. the ale input (p or t d pd0) latches the address . ref er to the memor y section f or additional 80c31 oper ating modes . 68hc11 figure 14 sho ws an interf ace to an 68hc11 where the psd7xx is configured in 8-bit m ultiple x ed mode with e and r/w settings . the ecspld can gener ate the read and wr signals f or e xter nal on board de vices . the cntl2 pin is not used and can be used as a pld input. 80c196 in figure 15, the intel 80c196 microcontroller , which has a m ultiple x ed sixteen-bit b us , is sho wn connected to a psd7xx. the bhe signal is used f or high data b yte selection. p or t pins can be configured in the psdabel as pld outputs to control the read y and b uswidth pins of the 80c196. mc68331 figure 16 sho ws a motorola mc68331 with non-m ultiple x ed sixteen-bit data b us and 24-bit address b us . the data b us from the mc68331 is connected to p or t a (d 0 7) and p or t b (d 8 15). the siz0 and a0 inputs deter mine the high/lo w b yte selection. 80c51xa the philips 80c51xa microcontroller f amily has an 8 or 16 bit m ultiple x ed b us that suppor ts b urst cycles . address bits a[3:0] are not m ultiple x ed while a[19:4] are m ultiple x ed with data bits d[15:0] in 16-bit mode . in 8-bit mode , a[11:4] are m ultiple x ed with data bits d[7:0]. the 80c51xa can be configured to oper ate with a psd7xx in 8-bit (sho wn in figure 17) or 16-bit (sho wn in figure 18) data mode . with a 16-bit data b us , the 80c51xa s wrh pin is connected to the pc7 pin on the psd7xx. pin p a0 is g rounded and not used. the 80c51xa impro v es b us throughput and perf or mance b y e x ecuting burst cycles to f etch codes from memor y . in burst cycles , address a1 9 4 are latched inter nally b y the psd7xx, while the 80c51xa changes the a 3 0 lines to sequentially f etch up to 16 b ytes of code . the psd access time is then measured from address a 3 a0 v alid to data in v alid. the psd7xx b us timing requirement in burst cycle is identical to the nor mal b us cycle e xcept the address set up or hold time with respect to ale is not required. bus inter face (cont.)
psd7xx family 13-32 bus inter face (cont.) 80c251 the intel 80c251 microcontroller f eatures a user-configur ab le b us interf ace with f our possib le b us configur ations as sho wn in t ab le 19. configuration 80c251 connecting page mode read/w rite to psd7xxe1 pins pins 1 wr cntl0 non-p age mode , 80c31 compatib le rd cntl1 a [ 7:0 ] m ultiple x with d [ 7:0 } psen cntl2 2 wr cntl0 non-p age mode psen only cntl1 a [ 7:0 ] m ultiple x with d [ 7:0 } 3 wr cntl0 p age mode psen only cntl1 a [ 15:8 ] m ultiple x with d [ 7:0 } 4 wr cntl0 p age mode rd cntl1 a [ 15:8 ] m ultiple x with d [ 7:0 } psen cntl2 t able 19. 80c251 configurations configur ation 1 is 80c31 compatib le . the b us interf ace to the psd7xx is identical to that sho wn in figure 13. configur ations 2 and 3 ha v e the same b us connection as sho wn in figure 19 . there is only one read input (psen) connected to the cntl1 pin on the psd7xx. the a16 connection to the p a0 pin allo ws f or a larger address input to the psd7xx. configur ation 4 is sho wn in figure 20. the rd signal is connected to cntl 1 and the psen signal is connected to the cntl2. the 80c251 has tw o major oper ating modes: p age mode and non-p age mode . in non-p age mode , the data is m ultiple x ed with the lo w er address b yte . the ale is activ e in e v er y b us cycle . in p age mode , data d[7:0] is m ultiple x ed with address a[15:8]. in a b us cycle where there is a p age hit, the ale signal is not activ e and only addresses a[7:0] are changing. the psd7xx suppor ts both modes . in p age mode , the psd b us timing is identical to non-p age mode e xcept the address hold time and setup time with respect to ale is not required. the psd7xx access time is measured from address a[7:0] v alid to data in v alid. upon po w er up the 80c251 accesses data at addresses fff8h and fff9h where the b us configur ation b ytes reside . after the configur ation register is set, the 80c251 star ts e x ecuting codes from location 0000h. the 7th epr om b loc k in the psd7xx has tw o chip selects , es7a and es7b . the second chip select, (es7b) can be defined to occup y the configur ation b yte locations while es7a is assigned to a diff erent memor y space .
psd7xx family 13-33 ea/vp x1 x2 reset rst out ( rst out ) ( ceout ) ( vstbyon ) ( rst out ) ( vtp ) int0 int1 t0 t1 p1.0 p1.1 p1.2 p1.3 p1.4 p1.5 p1.6 p1.7 p0.0 p0.1 p0.2 p0.3 p0.4 p0.5 p0.6 p0.7 pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 pc0 ( vstby ) pc2 pc1 pc3 pc4 pc5 pc6 pc7 p2.0 p2.1 p2.2 p2.3 p2.4 p2.5 p2.6 p2.7 adio0 adio1 adio2 adio3 adio4 adio5 adio6 adio7 adio8 adio9 adio10 adio11 adio12 adio13 adio14 adio15 cntl0 (wr) cntl1(rd) cntl2 (psen) pd0-ale pd1 pd2 reset rd wr psen ale/p txd rxd 29 28 27 25 24 23 22 21 30 39 31 19 18 9 12 13 14 15 1 2 3 4 5 6 7 8 38 37 36 35 34 33 32 ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 31 32 33 34 35 36 37 39 40 41 42 43 44 45 46 47 48 50 49 10 9 8 7 6 5 4 3 2 52 51 20 19 18 17 14 13 12 11 psd7xx 80c31 ad [ 7:0 ] ad [ 7:0 ] 21 22 23 24 25 26 27 28 17 16 29 30 a8 a9 a10 a11 a12 a13 a14 a15 rd wr psen ale 11 10 * v cc figur e 13. inter facing the psd7xx with an 80c31 mcu bus inter face (cont.) * if not used, reset pin m ust be pulled high.
psd7xx family 13-34 bus inter face (cont.) 9 10 11 12 13 14 15 16 adio0 adio1 adio2 adio3 ad104 ad105 adio6 adio7 adio8 adio9 adio10 adio11 ad1012 ad1013 adio14 adio15 cntl0 (r / w) cntl1(e) cntl 2 pd0 as pd1 pd2 reset 20 21 22 23 24 25 3 5 4 6 42 41 40 39 38 37 36 35 ad0 ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 a8 a9 a10 a14 a15 a13 a11 a12 ad1 ad2 ad3 ad4 ad5 ad6 ad7 e as r / w xt ex reset irq xirq pa0 pa1 pa2 pe0 pe1 pe2 pe3 pe4 pe5 pe6 pe7 vrh vrl pa3 pa4 pa5 pa6 pa7 pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 pc0 pc1 pc2 pc3 pc4 pc5 pc6 pc7 pc0 pc1 pc3 pc4 pc5 pc6 pc7 pd0 pd1 pd2 pd3 pd4 pd5 moda e as r / w 31 30 31 32 33 34 35 36 37 39 40 41 42 43 44 45 46 48 8 9 10 49 50 47 8 7 17 19 18 34 33 32 43 44 45 46 47 48 49 50 52 51 30 29 28 27 29 28 27 25 24 23 22 21 20 19 18 17 14 13 12 11 pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 7 6 5 4 3 2 52 51 modb 2 68hc11 psd7xx ad[7:0] ad[7:0] rst out ( rst out ) ( ceout ) ( vstbyon ) ( rst out ) ( vtp ) ( vstby ) pc2 * v cc v cc figur e 14. inter facing the psd7xx with a 68hc11 * if not used, reset pin m ust be pulled high.
psd7xx family 13-35 adio0 adio1 adio2 adio3 ad104 ad105 adio6 adio7 adio8 adio9 adio10 adio11 ad1012 ad1013 adio14 adio15 cntl0 ( wr ) cntl1 ( rd ) cntl 2(bhe) pd0- ale pd1 pd 2 reset 59 58 57 56 55 48 52 12 60 59 58 57 56 55 54 53 51 50 49 48 47 46 45 61 40 41 62 rd wr bhe ale 63 65 ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 ad8 ad9 ad10 ad14 ad15 ad13 ad11 ad12 p2.0/ txd p2.1/rxd p2.2/exint p2.3/ t2clk p2.4/ t2rst p2.5/ pwm p2.6/ t2up-dn p2.7/ t2cap hsi.0 hsi.1 hsi.2/hso.4 hsi.3/hso.5 angnd ea p3.0/ad 0 x1 x2 p3.1/ad1 p3.2/ad 2 p3.3/ad 3 p3.4/ad 4 p3.5/ad 5 p3.6/ad 6 p3.7/ad 7 p4.0/ad 6 p4.1/ad 9 p4.2/ad10 p4.3/ad11 p4.4/ad12 p4.5/ad13 p4.6/ad14 p4.7/ad15 rd wr bhe ale inst pc 0 pc1 pc 3 pc 4 pc 5 pc 6 pc 7 clkout p1.3 p1.2 p1.1 p1.0 p1.4 p1.5 47 46 50 49 44 43 p1.6 p1.7 hso.0 hso.1 hso.2 hso.3 30 31 32 33 34 35 36 37 39 40 41 42 43 44 45 46 48 8 9 10 49 50 47 18 17 15 44 42 39 33 38 ach 0/p0.0 ach1/p0.1 ach 2/p0.2 ach 3/p0.3 ach 4/p0.4 ach 5/p0.5 pcs6/p0.6 pcs7/p0.7 6 5 7 4 11 11 10 8 9 nmi ready cde buswidth reset 3 43 14 64 16 24 25 26 27 vref 13 12 29 28 27 25 24 23 22 21 20 19 18 17 14 13 12 11 pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 pa 0 pa1 pa 2 pa 3 pa 4 pa 5 pa 6 pa 7 7 6 5 4 3 2 52 51 2 80196 psd7xx d [ 15:0 ] d [ 15:0 ] rst out ( rst out ) ( ceout ) ( vstbyon ) ( rst out ) ( vtp ) ( vstby ) pc2 * v cc v cc figur e 15. inter facing the psd7xx to an 80c196 bus inter face (cont.) * if not used, reset pin m ust be pulled high.
psd7xx family 13-36 adio0 adio1 adio2 adio3 ad104 ad105 adio6 adio7 adio8 adio9 adio10 adio11 ad1012 ad1013 adio14 adio15 cntl0 ( r / w ) cntl1 ( ds ) cntl 2 ( si z0 ) pd0 as pd1 pd2 reset 121 122 123 124 125 81 80 32 90 20 21 22 23 24 25 26 27 30 31 33 35 36 37 38 41 42 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a14 a15 a13 a11 a12 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a16 a17 a18 a15 a13 a14 d8 d9 d10 d11 d12 d13 d14 d15 reset irq1 irq2 irq3 irq4 irq5 irq6 irq7 a1 a0 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 a17 a18 a19_cs6 a20_cs7 a21_cs8 a22_cs9 a23_cs10 as r / w ds pc0 pc1 pc3 pc4 pc5 pc6 pc7 siz0 siz0 siz1 clkout csboot br_cs0 bg_cs1 66 82 79 85 112 113 114 115 118 119 120 bgack_cs2 fc0_cs3 fc1_cs4 fc2_cs5 30 31 32 33 34 35 36 37 39 40 41 42 43 44 45 46 48 8 9 10 49 50 47 100 99 98 97 94 93 92 91 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 d0 d1 d2 d3 d4 d5 d6 d7 111 110 109 108 105 104 103 102 29 28 27 25 24 23 22 21 20 19 18 17 14 13 12 11 pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 7 6 5 4 3 2 52 51 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 psd7xx mc68331 a [ 18:0 ] a [ 18:0 ] d [ 15:0 ] d [ 15:0 ] 77 76 75 74 73 72 71 dsack0 dsack1 89 68 88 as r / w ds rst out ( rst out ) ( ceout ) ( vstbyon ) ( rst out ) ( vtp ) ( vstby ) pc2 * v cc figur e 16. inter facing the psd7xx to the mc68331 bus inter face (cont.) * if not used, reset pin m ust be pulled high.
psd7xx family 13-37 adio0 adio1 adio2 adio3 ad104 ad105 adio6 adio7 adio8 adio9 adio10 adio11 ad1012 ad1013 adio14 adio15 cntl0 ( wr ) cntl1 ( rd ) cntl 2 (psen ) pd0-ale pd1 pd2 reset 31 33 36 2 3 4 5 43 42 41 40 39 38 37 24 25 26 27 28 29 30 a4d0 a5d1 a6d2 a7d3 a8d4 a9d5 a10d6 a11d7 a12 a13 a14 a18 a19 a17 a15 a16 a0 a1 a2 a3 a4d0 a5d1 a6d2 a7d3 a8d4 a9d5 a10d6 a11d7 a12 a16 a17 a18 a19 a15 a13 a14 txd1 t2ex t2 t0 rst ea/ wait busw a1 a0/wrh a2 a3 a4d0 a5d1 a6d2 a7d3 a8d4 a9d5 a10d6 a11d7 a12d8 a13d9 a14d10 a15d11 a16d12 a17d13 a18d14 a19d15 psen rd wrl pc0 pc1 pc3 pc4 pc5 pc6 pc7 ale psen rd wr ale 32 19 18 30 31 32 33 34 35 36 37 39 40 41 42 43 44 45 46 48 8 9 10 49 50 47 7 9 8 16 xtal1 xtal2 rxd0 txd0 rxd1 21 20 11 13 6 29 28 27 25 24 23 22 21 20 19 18 17 14 13 12 11 pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 7 6 5 4 3 2 52 51 a0 a1 a2 a3 80c51xa psd7xx 35 17 int0 int1 14 10 15 * rst out ( rst out ) ( ceout ) ( vstbyon ) ( rst out ) ( vtp ) ( vstby ) pc2 v cc figur e 17. inter facing the psd7xx to the 80c51xa, 8-bit data bus bus inter face (cont.) * if not used, reset pin m ust be pulled high.
psd7xx family 13-38 adio0 adio1 adio2 adio3 ad104 ad105 adio6 adio7 adio8 adio9 adio10 adio11 ad1012 ad1013 adio14 adio15 cntl0 ( wr ) cntl1 ( rd ) cntl 2 (psen ) pd0 - ale pd1 pd2 reset 31 33 37 2 3 4 5 43 42 41 40 39 38 36 24 25 26 27 28 29 30 a4d0 a5d1 a6d2 a7d3 a8d4 a9d5 a10d6 a11d7 a12d8 a13d9 a14d10 a18d14 a19d15 a17d13 a15d11 a16d12 wrh a1 a2 a3 a4d0 a5d1 a6d2 a7d3 a8d4 a9d5 a10d6 a11d7 a12d8 a16d12 a17d13 a18d14 a19d15 a15d11 a13d9 a14d10 txd1 t2ex t2 t0 rst ea/wait busw a1 a0/wrh a2 a3 a4d0 a5d1 a6d2 a7d3 a8d4 a9d5 a10d6 a11d7 a12d9 a13d9 a14d10 a15d11 a16d12 a17d13 a18d14 a19d15 psen rd wrl ale psen rd wr ale 32 19 18 30 31 32 33 34 35 36 37 39 40 41 42 43 44 45 46 48 8 9 10 49 50 47 7 9 8 16 xtal1 xtal2 rxd0 txd0 rxd1 21 20 11 13 6 29 28 27 25 24 23 22 21 20 19 18 17 14 13 12 11 pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 7 6 5 4 3 2 52 51 a1 a2 a3 80c51xa psd7xx 35 17 int0 int1 14 10 15 wrh rst out * pc0 pc1 pc3 pc4 pc5 pc6 pc7 ( rst out ) ( ceout ) ( vstbyon ) ( rst out ) ( vtp ) ( vstby ) pc2 v cc v cc figur e 18. inter facing the psd7xx to the 80c51xa, 16-bit data bus bus inter face (cont.) * if not used, reset pin m ust be pulled high.
psd7xx family 13-39 adio0 adio1 adio2 adio3 ad104 ad105 adio6 adio7 adio8 adio9 adio10 adio11 ad1012 ad1013 adio14 adio15 cntl0 ( wr ) cntl1 ( rd ) cntl 2(psen) pd0- ale pd1 pd2 reset 32 26 43 42 41 40 39 38 37 36 24 25 27 28 29 30 31 33 a0 a1 a2 a3 a4 a5 a6 a7 ad8 ad9 ad10 ad14 ad15 ad13 ad11 ad12 a0 a1 a2 a3 a4 a5 a6 a7 ad8 ad9 ad10 ad11 ad15 ale wr a16 rd ad14 ad12 ad13 14 9 2 3 4 5 6 7 8 21 20 11 13 p1.0 p1.1 p1.2 p1.3 p1.4 p1.5 p1.6 p1.7 p3.0/ rxd p3.1/ txd p3.2/ int0 x2 x1 p3.3/ int1 rst ea a16 ** p0.1 p0.0 p0.2 p0.3 p0.4 p0.5 p0.6 p0.7 p2.0 p2.1 p2.2 p2.3 p2.4 p2.5 p2.6 p2.7 ale psen wr rd / a16 19 18 30 31 32 33 34 35 36 37 39 40 41 42 43 44 45 46 48 8 9 10 49 50 47 29 28 27 25 24 23 22 21 20 19 18 17 14 13 12 11 pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 7 6 5 4 3 2 52 51 80c251sb psd7xx 35 p3.4/ t0 p3.5/ t1 16 15 17 10 * rst out v cc pc0 pc1 pc3 pc4 pc5 pc6 pc7 ( rst out ) ( ceout ) ( vstbyon ) ( rst out ) ( vtp ) ( vstby ) pc2 figur e 19. inter facing the psd7xx to the 80c251, with one read input bus inter face (cont.) * * if not used, reset pin m ust be pulled high. ** a16 is optional.
psd7xx family 13-40 adio0 adio1 adio2 adio3 ad104 ad105 adio6 adio7 adio8 adio9 adio10 adio11 ad1012 ad1013 adio14 adio15 cntl0 ( wr ) cntl1 ( rd ) cntl 2 ( psen) pd0- ale pd1 pd2 reset 32 26 43 42 41 40 39 38 37 36 24 25 27 28 29 30 31 33 a0 a1 a2 a3 a4 a5 a6 a7 ad8 ad9 ad10 ad14 ad15 ad13 ad11 ad12 a0 a1 a2 a3 a4 a5 a6 a7 ad8 ad9 ad10 ad11 ad15 ale wr psen rd ad14 ad12 ad13 14 9 2 3 4 5 6 7 8 21 20 11 13 p1.0 p1.1 p1.2 p1.3 p1.4 p1.5 p1.6 p1.7 p3.0/rxd p3.1/txd p3.2/int0 x2 x1 p3.3/int1 rst ea p0.1 p0.0 p0.2 p0.3 p0.4 p0.5 p0.6 p0.7 p2.0 p2.1 p2.2 p2.3 p2.4 p2.5 p2.6 p2.7 ale psen wr rd/a16 pc0 pc1 pc3 pc4 pc5 pc6 pc7 19 18 30 31 32 33 34 35 36 37 39 40 41 42 43 44 45 46 48 8 9 10 49 50 47 29 28 27 25 24 23 22 21 20 19 18 17 14 13 12 11 pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 7 6 5 4 3 2 52 51 80c251sb psd7xx 10 35 p3.4/t0 p3.5/t1 16 15 17 rst out ( rst out ) ( ceout ) ( vstbyon ) ( rst out ) ( vtp ) ( vstby ) pc2 * v cc figur e 20. inter facing the psd7xx to the 80c251, with read and psen input bus inter face (cont.) * if not used, reset pin m ust be pulled high.
psd7xx family 13-41 i/o por ts there are f our prog r ammab le i/o por ts: p or ts a, b are 8 bits , p or t c is se v en bits and p or t d is three bits . the por ts can be configured to function in diff erent modes of oper ation. each por t pin is individually configur ab le allo wing a single por t to perf or m m ultiple functions . the configur ation is defined either using the psdsoft tools or b y the microcontroller wr iting to the on-chip registers . general por t ar chitectur e the gener al architecture of the i/o p or t is sho wn in figure 21. individual p or t diag r ams are sho wn in figures 23, 24 and 25, and will be discussed in the section belo w . if the psd7xx is configured to a non-m ultiple x ed b us mode , p or t a and/or p or t b are connected to the mcu data b us and are not a v ailab le as gener al pur pose i/o por ts . as sho wn in figure 21, the por t pins contain an output m ultiple x er whose selects are dr iv en b y the configur ation defined in psdabel and the control registers . inputs to the m ultiple x er include the f ollo wing: o output data from the data out register in the mcu i/o output mode o latched address outputs o gpld micro ? cell output or ecspld e xter nal chip select output the abo v e inputs are also connected to the p or t data buff er (pdb) f or f eedbac k to the inter nal data bus that can be read b y the microcontroller . the pdb is a three-state b uff er oper ating lik e a m ultiple x er that allo ws only one source to be read at a time . the pdb also has inputs from the direction register , control register and direct por t pin input (data in). the p or t pin s tr i-state output dr iv er enab le is controlled b y a tw o input or gate whose inputs come from the gpld and arr a y enab le product ter m (.oe) and the direction register . if the enab le product ter m of the arr a y output is not defined, then the direction register has sole control of the b uff er . ref er to t ab les 20 and 21 on ho w the direction of a por t pin is configured. dir ection register bit por t pin mode 0 input 1 output t able 20. por t pin dir ection contr ol, output enable p .t . not defined dir ection register bit output enable p .t .* por t pin mode 0 0 input 0 1 output 1 0 output 1 1 output t able 21. por t pin dir ection contr ol, output enable p .t . defined * p or t d does not ha v e an output enab le p .t . the register contents can be altered b y the microcontroller . the pdb f eedbac k path allo ws the microcontroller to chec k the contents of the registers . the a, b and c p or ts ha v e embedded input micro ? cells which can be configured as a latch, a register or direct input to the gpld . the latch and register are cloc k ed b y the address strobe or a product ter m from the gpld and arr a y . the output from the input micro ? cell dr iv es the pld input b us and can be read b y the microcontroller . ref er to the input micro ? cell descr iption in the pld section. p or t a has additional logic (not sho wn in figure 21) that enab les it to oper ate in p er ipher al i/o mode when the pio bit in the vm register is set.
psd7xx family 13-42 internal data bus data out reg. d q d g q d q d q wr wr wr address micro cell outputs enable product term ( .oe ) ext.cs ale read mux p d b gpld - input control reg. dir reg. input micro cell enable out data in output select output mux port in data out address figur e 21. general i/o por t ar chitectur e i/o por ts (cont.)
psd7xx family 13-43 por t operating modes the i/o p or ts ha v e se v er al modes of oper ation as sho wn in t ab le 22. the mode ma y be selected using the psdabel tool and prog r ammed into the de vice using non-v olatile memor y (nvm) that is activ e when po w er is applied and cannot be altered unless the de vice is reprog r ammed. if a mode is not defined in psdsoft, then other modes can be set b y the microcontroller wr iting to the p or t configur ation registers . the pld i/o , data p or t address input and super visor y function modes are nvm configur ations . the other modes are initiated b y the microcontroller . if the nvm modes are not selected, the por t can be altered dynamically betw een mcu i/o or address out modes b y wr iting to the control register . each bit of the eight-bit control register ma y store a ?? setting its respectiv e bit in the por t to mcu i/o , or to a ?? setting it to address out. the direction register or the output enab le product ter m deter mine if the pin is input or output. t ab le 22 summar iz es the oper ating modes of the i/o por ts . not all the functions are a v ailab le to e v er y por t. t ab le 23 sho ws ho w and where the diff erent modes are configured. por t mode por t a por t b por t c por t d mcu i/o y es y es y es y es pld i/o mcellab outputs p a 7 4 pb 7 4 no no mcellc outputs no no pc 7 0 no ecspld outputs p a 3 0 pb 3 0 no pd 2 0 pld inputs y es y es y es y es address out y es (a 7 0) y es (a 7 0, a1 5 8) no no address in y es y es y es no data p or t y es (d7 0) y es (d1 5 8) no no open dr ain y es (p a7 4) y es (pb7 4) y es no sle w rate y es (p a3 0) y es (pb3 0) no y es p er ipher al i/o y es no no no super visor y function no no y es no t able 22. por t operating modes i/o por ts (cont.)
psd7xx family 13-44 i/o por ts (cont.) contr ol dir ection vm defined in defined in register register register mode psdabel psdconfiguration setting setting setting mcu i/o declare pins only na 0 1 = output, na 0 = input (note 1) pld i/o logic equations na na* (note 1) na data p or t na specify b us type na na na (p or t a,b) address out declare pins only na 1 1 (note 1) na (p or t a,b) address in logic equation f or na na na na (p or t a,b ,c) input micro ? cells p er ipher al i/o logic equations na na na pio bit = 1 (p or t a) (psel0 & 1) super visor y logic equations 1. specify cloc k na na na function (wdog_en and source wdog_clr) 2. w atchdog configur ation 3. reset output 4. ref erence v oltage le v el 5. standb y v oltage configur ation t able 23. por t operating mode settings * na ?not applicab le no te 1: the direction of the p or t a, b , c pins are controlled b y the direction register ored with the individual output enab le product ter m (.oe) from the gpld and arr a y . por t operating modes (cont.)
psd7xx family 13-45 pld i/o mode the pld i/o mode uses the por t as an input to the gpld input micro ? cell, and/or as an output from the gpld , ecspld . the p or t assignments are sho wn in t ab les 10 and 11. the output can be tr i-stated with a control signal defined b y a product ter m (.oe) from the pld , or , b y setting a z ero in the direction register . the direction register m ust not be set to ??if the pin is defined as a pld input pin. the pld i/o mode is specified in psdabel b y declar ing the por t pins , then wr iting an equation assigning it to the por t. mcu i/o mode in the mcu i/o mode the microcontroller uses the psd7xx por ts to e xpand its o wn i/o por ts . the por ts on the psd7xx are mapped into the microcontroller address space . the addresses of the por ts are listed in t ab le 28. a por t pin will be put into mcu i/o mode b y wr iting a z ero to the corresponding bit in the control register . the direction ma y be changed b y wr iting to the direction register f or the por t where a ??mak es it an output and a ??an input. the output enab le product ter m also can change the direction of the pin (see t ab le 20 and 21). when the pin is configured as output, the content of the data out register dr iv es the pins . in input mode , the microcontroller reads the por t input through the data in b uff er p or ts c and d do not ha v e a control register and are in mcu i/o mode b y def ault f or pins that are not configured as pld i/o . addr ess out mode f or microcontrollers with a m ultiple x ed address/data b us , the por ts in address out mode dr iv e latched addresses to e xter nal de vices . address [7:0] are alw a ys assigned to p or t a. see t ab le 29 f or the address output pin assignments on p or ts a and b . the direction register and the control register m ust be set to a ??f or por t pins using address out mode . in non-m ultiple x ed 8 bit b us mode , address[7:0] are a v ailab le on p or t b in address out mode . i/o por ts (cont.)
psd7xx family 13-46 i/o por ts (cont.) por t operating modes (cont.) addr ess in mode f or microcontrollers that ha v e more than 16 address lines , the higher addresses can be connected to p or t a, b , or c . the address input can be latched in the input micro ? cell b y ale. an y input that is included in the dpld equations f or the psd epr om and sram is considered as address input. data por t mode p or t a and b can be used as data b us por ts f or a microcontroller with a non-m ultiple x ed address/data b us . the data p or t is connected to the data b us of the microcontroller . the gener al i/o functions are disab led in p or t a or b if the por t is configured as data p or t. super visor y function mode p or t c (pins pc 1 pc6) can be configured to implement the super visor y function. ref er to the super visor y section f or a detailed descr iption. peripheral i/o mode only p or t a suppor ts the p er ipher al i/o mode where all of p or t a i/o ser v es as a tr i-state capab le bi-directional data b uff er of the microcontroller s data b us . p er ipher al mode is enab led b y setting bit 7 of the vm register to a ?? figure 22 sho ws that when p er ipher al mode is enab led and either psel0 and psel1 from the dpld is activ e , p or t a acts as a bi-directional b uff er f or the microcontroller d[7:0] data b us . the b uff er is tr i-stated when psel 0 or 1 is not activ e . the p er ipher al i/o mode can be used to interf ace with e xter nal per ipher als . open drain/slew rate mode p or ts a (pins p a7-4) and b (pins pb7-4) and c can be configured as an open dr ain instead of cmos outputs . the open dr ain configur ation is useful f or sinking large currents to oper ate leds , f or e xample . the open dr ain mode is enab led b y wr iting a ??to the corresponding bit in the dr iv e register . p or t a (p a 3 0), p or t b (pb 3 0) and p or t d can be configured as ecspld outputs that ha v e a high sle w r ate . the high sle w r ate is enab led b y wr iting a ??to the corresponding bit in the dr iv e register . rd psel0 psel1 vm register bit 7 wr pa0 - pa7 d0 - d7 data bus figur e 22. por t a peripheral mode
psd7xx family 13-47 i/o por ts (cont.) por t registers each por t has a set of registers used f or configur ation (pcr, p or t configur ation registers) and data tr ansf ers (pdr, p or t data registers). the contents of the registers can be accessed b y the microcontroller through nor mal read/wr ite b us cycles at the addresses giv en in t ab les 28 and 28a. the register addresses are compr ised of the csiop output from the dpld plus an address offset as listed in the tab les . the pins of a por t are individually configur ab le and each bit in the register controls its respectiv e pin. f or e xample , bit 0 in a register ref ers to bit 0 in its por t. the three p or t configur ation registers , sho wn in t ab le 24, are used f or setting the por t configur ation. each register is set to z ero at po w er up . register name por t mcu access control a,b wr ite/read direction a,b ,c ,d wr ite/read dr iv e* a,b ,c ,d wr ite/read t able 24. por t configuration registers * note: see t ab le 25 f or dr iv e register bit definition. contr ol register a z ero in the control register sets the p or t pin to mcu i/o f or p or t a and b . a ??sets the p or t pin to address out mode . the def ault mode is mcu i/o . dir ection register controls the direction of data flo w in the i/o p or ts . a ??configures the por t to be an output, and a ??to an input. the i/o configur ation can be read from the direction register . the def ault mode is input. as sho wn in the p or t architecture diag r am, the direction of data flo w in p or t a,b and c pins are also controlled b y the output enab le (.oe) product ter m from the gpld and arr a y . if the .oe product ter m is not activ e , the direction register has sole control of the pin direction. an e xample of a configur ation f or a por t with the three least significant bits set to output and the remainder set to input is sho wn in t ab le 25. the p or t d register has only the three least significant bits activ e . bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 0 0 0 0 1 1 1 t able 25. por t dir ection assignment example
psd7xx family 13-48 i/o por ts (cont.) por t registers (cont.) drive register the dr iv e register configures the pin dr iv er as open dr ain, or in the case of ecspld outputs , sets the pin to oper ate in high sle w r ate . an e xter nal pull-up resistor is not required when the pin is in the sle w r ate mode . f or p or ts a and b the register sets diff erent functions f or the lo w er and higher nib b les . the f our upper bits set the corresponding bits as cmos (? ) or open dr ain (? ) dr iv er . the f our lo w er bits are used f or sle w r ate control. the sle w r ate is a measurement of the r ise and f all times of the output. a higher sle w r ate means a f aster output response while a lo w er sle w r ate is a slo w er , lo w er slope , response . the pin oper ates in high sle w r ate when the corresponding bit in the dr iv e register is set to ?? t ab le 26 sho ws the dr iv e registers of p or t a, b , c and d and which pin has the open dr ain or sle w rate configur ation. drive bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register p or t a open open open open sle w sle w sle w sle w dr ain dr ain dr ain dr ain rate rate rate rate p or t b open open open open sle w sle w sle w sle w dr ain dr ain dr ain dr ain rate rate rate rate p or t c open open open open open open open open dr ain dr ain dr ain dr ain dr ain dr ain dr ain dr ain p or t d na na na na na sle w sle w sle w rate rate rate t able 26. drive register pin assignment no te: na = not applicab le , bit should set to ??
psd7xx family 13-49 i/o por ts (cont.) por t data registers the p or t data registers , sho wn in t ab le 27, are used b y the microcontroller to wr ite or read data to or from the por ts . t ab le 27 sho ws the register name , the por ts ha ving each register type and microcontroller access f or each register . the registers are descr ibed belo w . register name por t mcu access data in a,b ,c ,d read ?the input on pin data out a,b ,c ,d wr ite/read output micro ? cell a,b ,c read ?outputs of micro ? cells wr ite ?loading micro ? cells flip-flop input micro ? cell a,b ,c read ?outputs of the input micro ? cells enab le out a,b ,c read ?the output enab le control of the por t dr iv er t able 27. por t data registers data in p or t pins are connected directly to the data in b uff er . in mcu i/o input mode , the pin input is read through the data in b uff er . data out register stores output data wr itten b y the mcu in the mcu i/o output mode . the contents of the register are dr iv en out to the pins if the direction register or the .oe product ter m is set to ?? the contents of the register can also be read bac k b y the microcontroller . output micr o ? cell the gpld output micro ? cells occup y a location in the microcontroller s address space . the microcontroller can read the output of the micro ? cells . wr iting to the micro ? cell loads data to the micro ? cell flip-flops . ref er to the pld section f or more detail. input micr o ? cell the input micro ? cells can be used to latch or store e xter nal inputs . the outputs of the input micro ? cells are routed to the pld input b us and also can be read b y the microcontroller . ref er to the pld section f or detail descr iption. enable out the enab le out b uff er allo ws the microcontroller to read the outputs of the ?r?gate that is the enab le input to the por t output dr iv er . a ??indicates the dr iv er is in output mode , a ? indicates the dr iv er is in tr i-state and the pin is in input mode .
psd7xx family 13-50 i/o por ts (cont.) por t data registers (cont.) register i/o addr ess of fset the base address of the registers is defined in the csiop equation that occupies 256 b ytes of address space and is defined b y the user in psdsoft. the lo w er address b yte a[7:0], or address offset, selects the register . t ab le 28 sho ws the address offset f or all mcus e xcept those motorola microcontrollers with a 16-bit data b us . t ab le 28a sho ws the address offset f or motorola mcus in 16-bit mode . f or e xample , when the csiop is defined to occup y the address r ange of 1000h to 10ffh in psdabel, the address of the p or t a control register is then 1002h. register name por t a por t b por t c por t d data in 00 01 10 11 control 02 03 data out 04 05 12 13 direction 06 07 14 15 dr iv e 08 09 16 17 input micro ? cell 0a 0b 18 enab le out 0c 0d 1a output micro ? cell 20 20 21 t able 28. i/o register addr ess of fset (r elative to csiop) register name por t a por t b por t c por t d data in 01 00 11 10 control 03 02 data out 05 04 13 12 direction 07 06 15 14 dr iv e 09 08 17 16 input micro ? cell 0b 0a 19 enab le out 0d 0c 1b output micro ? cell 21 21 20 t able 28a. register addr ess of fset for 16-bit motor ola micr ocontr ollers in 16-bit mode (r elative to csiop)
psd7xx family 13-51 i/o por ts (cont.) micr ocontr oller por t a (3:0) por t a (7:4) por t b (3:0) por t b (7:4) 8051xa (8-bit) n/a* address (7:4) address (11:8) n/a 80c251 (p age mode) n/a n/a address (11:8) address (15:12) all other 8-bit multiple x ed address (3:0) address (7:4) address (3:0) address (7:4) 8051xa (16-bit) n/a address (7:4) address (11:8) address (15:12) all other 16-bit address (3:0) address (7:4) address (11:8) address (15:12) multiple x ed 8-bit non-multiple x ed bus n/a n/a address (3:0) address (7:4) t able 29. i/o por t latched addr ess output assignments por t a and b ? functionality and str uctur e p or t a and b ha v e similar functionality and str ucture as sho wn in figure 23. the tw o por ts can be configured to perf or m one or more of the f ollo wing functions: o mcu i/o mode o gpld output micro ? cells mcella b [ 7: 4 ] can be connected to p or t a p a [ 7: 4 } or p or t b p b [ 7: 4 ]. o ecspld output exter nal chip select output can be connected to either p or t a p a[3:0] or p or t pb[3:0]. o latched address output ? pro vide latched address output per t ab le 29. o address in ? additional high address inputs using the input micro ? cells . o open dr ain/sle w rate pins p a[3:0] and pb[3:0] can be configured to open dr ain mode pins p a [7: 4 ] and pb [ 7: 4 ] can be configured to f ast sle w r ate o data p or t p or t a to d [ 7:0} f or 8 bit non-m ultiple x ed b us p or t b to d[15: 8 ] f or 16-bit non-m ultiple x ed b us o p er ipher al mode ? p or t a only n/a = not applicab le .
psd7xx family 13-52 i/o por ts (cont.) internal data bus data out reg. d q d g q d q d q wr wr wr address mcell ab [ 7:4 ] enable product term ( .oe ) ecs [ 3:0 ] ale read mux p d b gpld - input control reg. dir reg. input micro cell enable out data in output select output mux port a or b pin data out address a [ 7: 0 ] or a [ 15: 8 ] figur e 23. por t a and b str uctur e
psd7xx family 13-53 i/o por ts (cont.) por t c ? functionality and str uctur e p or t c does not suppor t address out mode and the control register is not required. p or t c can be configured to perf or m one or more of the f ollo wing functions: o mcu i/o mode o gpld output ? mcellc outputs can be connected to p or t c pins o gpld input ? via the eight input micro ? cells o address in ? additional high address inputs using the input micro ? cells . o open dr ain ? p or t c pins can be configured in open dr ain mode o super visor y function ?p or t c (pc1 ?pc6) pins can be configured to perf or m the super visor y function. pin pc7 ma y be configured as the wrh input in cer tain microcontroller interf ace designs . por t d ? functionality and str uctur e p or t d has only three i/o pins , does not suppor t address out mode , and no control register is required. p or t d can be configured to perf or m one or more of the f ollo wing functions: o mcu i/o mode o ecspld output ? exter nal chip select output o pld input ? direct input to pld , no input micro ? cells o sle w r ate ? pins can be set up f or f ast sle w r ate p or t d pins can be configured in psdsoft as input pins f or other dedicated functions: o pd0 ? ale, as address strobe input o pd1 ? clkin, as cloc k input to the micro ? cells flip-flops and apd counter o pd2 ? csi, as activ e lo w chip select input. a high input will disab le the psd epr om/sram.
psd7xx family 13-54 i/o por ts (cont.) internal data bus data out reg. d q d q wr wr mcell c [ 7: 0 ] enable product term ( .oe ) read mux p d b gpld - input dir reg. input micro cell enable out data in output select output mux supervisory function port c pin data out figur e 24. por t c str uctur e
psd7xx family 13-55 i/o por ts (cont.) internal data bus data out reg. d q d q wr wr ecs [ 6:4 ] read mux p d b gpld - input dir reg. data in output select output mux port d pin data out figur e 25. por t d str uctur e
psd7xx family 13-56 the psd7xx has inter nal epr om and sram memor y b loc ks . the memor y select signals come from the dpld and are user-defined in the psdsoft softw are . eprom the psd7xx pro vides three epr om densities: 256k bit, 512k bit or 1m bit. the epr om is divided into eight b loc ks . the epr om can be configured as 32k x 8, 64k x 8 or 128k x 8 f or eight-bit data b usses and 16k x 16, 32k x 16 or 64k x 16 f or 16-bit data b uses . each b loc k has its o wn epr om select. bloc ks z ero to six ha v e one select (es0-es6) and b loc k 7 has tw o selects , es7a and es7b , either of which enab les bloc k 7. the dual selects allo w bloc k 7 to reside in tw o separ ate memor y spaces . a typical application w ould be to store an mcu reset v ector residing in the memor y space and accessed b y es7b . the rest of the bloc k 7 memor y space w ould be accessed b y es7a. the same technique can also be used to store the configur ation b ytes of the intel 80251 microcontroller which reside at the high end of the memor y space . sram the sram has 4k bits of memor y that can be configured as 512 x 8 or 256 x 16. the sram is enab led from the rs0 output of the dpld . the sram has a batter y bac k-up mode which is automatically in v ok ed when the supply v oltage drops under the standb y v oltage . sram wr ite protection is pro vided in bac k-up mode . memor y select map the epr om and sram select are outputs from the dpld whose equations are defined using psdabel. the f ollo wing r ules apply to the memor y space definitions: 1. epr om b loc k select space should not be larger than the ph ysical b loc k siz e 2. epr om b loc k select space m ust not o v er lap 3. sram, i/o and p er ipher al i/o spaces cannot o v er lap 4. sram, i/o and p er ipher al i/o spaces can o v er lap epr om with pr ior ity giv en to the sram or i/o . this allo ws the sram or i/o to utiliz e the epr om space that is not used. memor y blocks
psd7xx family 13-57 memor y blocks (cont.) page register the f our-bit p age register increases the addressing capability of the microcontroller b y a f actor of 16. the contents of the register can also be read b y the microcontroller . the outputs of the p age register (pgr0-pgr3) are inputs to the pld and can be included in the epr om or sram chip select equations . figure 26 sho ws the p age register . the f our flip-flops in the register are connected to the inter nal data b us d 0 d3. the microcontroller can wr ite to or read from the p age register . the register can oper ate as an independent register to the microcontroller if page mode is not implemented. reset d0 -d3 r / w d0 q0 q1 q2 q3 d1 d2 d3 page reg. pgr0 pgr1 pgr2 pgr3 dpld gpld ecspld es0 -7 rs0 pld figur e 26. page register for memor y bank switching security pr otection the psd7xx has a prog r ammab le secur ity bit which acts as a duplication barr ier . when the bit is set, the contents of the epr om, non-v olatile configur ation bits , and pld cannot be read b y de vice prog r ammers . the secur ity bit is set through the psdsoft design t ools and is embedded in the compiled output file . the secur ity bit is uv er asab le and a secured psd7xx in a windo w ed pac kage can be er ased and re-prog r ammed.
psd7xx family 13-58 bit 7 bit 6* bit 5* bit 4* bit 3* bit 2* bit 1 bit 0 pio_en rd_en psen_en 0 = disab le 0 = rd access 0 = psen access pio mode sram, i/o epr om only 1 = enab le 1 = rd access 1 = psen access pio mode epr om, epr om, sram, i/o sram, i/o t able 30. vm register * bit 6-2 are not used, set to ?? bits 7, 1 and 0 are set to ??after reset. memor y select for 8031 micr ocontr ollers the 8031 f amily of microcontrollers , including 80c251 and 80c51xa, has a separ ate address space f or code memor y (enab led b y psen) and data memor y (enab led b y rd). the psd7xx allo ws the epr om and sram to reside in the prog r am space , data space or both. three diff erent configur ations are possib le: o separate space mode code memor y space is separ ated from data memor y space . the psen signal is used to access the prog r am code from the epr om, and the rd signal is used to access data from the sram and i/o p or ts . this is the def ault configur ation. o combined space mode the prog r am and data memor y spaces are combined into one 64kb b loc k space that allo ws the epr om or sram to be accessed b y either psen or rd . the epr om and sram b loc ks address space m ust not o v er lap . this mode is enab led b y the microcontroller b y setting the bits in the vm register as sho wn in t ab le 30. if bit 0 is ?? either psen or rd can access the sram. if bit 1 is a ?? either rd or psen can access the epr om. figure 26 sho ws the memor y select logic f or combined space mode . o mixed mode allo ws individual epr om b loc ks to be configured in either data space or prog r am space . epr om b loc k chip selects m ust be qualified with the 8031 rd input in the es 0 es7 equations . an activ e lo w rd will select epr om b loc ks in data space and disab le the b loc ks that are in prog r am space . f or epr om b loc ks that reside in data space , the access time is calculated from rd v alid to data v alid. this mode is set automatically b y psdsoft whene v er the rd signal is included in the epr om chip select equations . memor y blocks (cont.)
psd7xx family 13-59 memor y blocks (cont.) dpld es0-es7 rs0 psen rd eprom sram cs cs oe oe figur e 27. 8031 memor y modes ? separate space mode dpld es0-es7 rs0 psen eprom sram oe oe rd rd vm reg bit 1 vm reg bit 0 figur e 28. 80c31 memor y mode ? combined space mode
psd7xx family 13-60 the psd7xx off ers a n umber of configur ab le po w er sa ving options which include the a utomatic p o w er do wn (apd) logic and the p o w er management mode registers (pmmr0 and pmmr1). the apd logic allo ws the psd7xx to enter into either p o w er do wn or sleep mode automatically , while the pmmrs can be configured at r un time b y the microcontroller to selectiv ely reduce the po w er consumption of the psd functional b loc ks . the apd logic and power down mode the a utomatic p o w er do wn (apd) logic puts the psd7xx into po w er sa vings mode b y monitor ing the activity of the address strobe (ale/as). if the apd unit is enab led, the f our-bit apd counter star ts counting whene v er the address strobe is inactiv e . if the strobe remains inactiv e f or fifteen clkin cloc k per iods , the po w er do wn (pdn) signal will become activ e and the psd7xx enter into either p o w er do wn or sleep mode . immediately after ale star ts pulsing the psd7xx will retur n to nor mal oper ation. the apd counter cloc k source comes from the clkin pin which is pin pd1 on p or t d or the super v_clk from the super visor y function. in order to guar antee that the apd counter will not o v erflo w when enab led, there should be less than 15 cloc ks betw een tw o successiv e ale pulses . usually , microcontrollers enter ing po w er do wn mode will freez e their ale at logic high or lo w le v el. by prog r amming bit 0 of pmmr0, the apd kno ws when the mcu is in po w er do wn mode . if the apd detects the ale le v el is in the po w er do wn state f or 15 clkin per iods , then the psd7xx will enter a po w er do wn mode . t o enab le the apd oper ation, the apd bit in the pmmr0 should be set to ?? when the address strobe star ts pulsing again, or the csi input s witches from high to lo w , the psd7xx will retur n to nor mal activity . when the pdn signal is set to ??(activ e state) in p o w er do wn (or sleep mode), the psd7xx mcu b us interf ace is disab led and all mcu inputs (address , data and control signals) are b loc k ed from enter ing the de vice . if the cloc k input to the pld is not needed in p o w er do wn mode , it should be b loc k ed to sa v e po w er b y setting bit 4 and 5 in the pmmr0 to ?? sleep mode the sleep mode is activ ated if the sleep mode bit, the apd bit and the ale p olar ity bit in the pmmrs are set, and the apd counter has o v erflo w ed after 15 clkin cloc ks (see figure 29). in sleep mode the psd7xx consumes less po w er than the p o w er do wn mode , with typical i cc reduced to 25 a. in this mode , the pld still monitors the inputs and responds to them. as soon as the ale star ts pulsing or the csi input s witches from high to lo w , the psd7xx e xits the sleep mode . the psd7xx access time from sleep mode is specified b y t l vd v1. the pld response time to an input tr ansition is specified b y t l vd v2. power management unit por t function pin level mcu i/o no change pld out no change address out undefined data p or t three-state p er ipher al i/o three-state t able 31. power down ef fect on por ts
psd7xx family 13-61 pld access pld recover y t ime recover y t ime t ypical pr opagation to nor mal access to nor mal standby mode delay operation t ime access cur r ent p o w er do wn nor mal t pd 0 no access t l vd v 50 a (note 1) (note 4) sleep t l vd v2 t l vd v3 no access t l vd v1 25 a (note 2) (note 3) (note 4) t able 32. summar y of psd7xx t iming and standby cur r ent during power down and sleep mode power management unit (cont.) no tes: 1. p o w er do wn does not aff ect the oper ation of the pld . 2. in sleep mode an y input to the pld will ha v e a propagation dela y of t l vd v2. 3. pld reco v er y time to nor mal oper ation after e xisting sleep mode . an input to the pld dur ing the tr ansition will ha v e a propagation dela y of t l vd v3. 4. t ypical current consumption assuming clkin is disab led. apd en pmmr0 bit 1 ale polarity pmmr0 bit 0 ale csi clkin apd clear logic edge detect apd counter power down ( pd ) disable bus interface eprom select sram select i/o select pd clr pd sleep mode sleep-en pmmr1 bit 1 disable eprom/sram zpld figur e 29. apd logic block
psd7xx family 13-62 apd disabled set ale polarity in pmmr0 bit 0 need sleep mode enable apd set pmmr0 bit 1 = 1 disable pld clkin set pmmr0 bit 4, 5 = 1 disable pld clkin set pmmr0 bit 4, 5 = 1 psd7xx in power down mode reset enable sleep mode set pmmr1 bit 1 enable apd set pmmr0 bit 1 = 1 psd7xx in sleep mode ale idle and 15 clkin clock ale idle and 15 clkin clock yes no figur e 30. enable power down flow char t power management unit (cont.)
psd7xx family 13-63 bit 0 0 = ale po w er do wn polar ity lo w 1 = ale po w er do wn polar ity high bit 1 0 = a utomatic p o w er do wn (apd) is disab led 1 = a utomatic p o w er do wn (apd) is enab led bit 2 0 = epr om/sram cmiser is off 1 = epr om/sram cmiser is on bit 4 0 = clkin input to the pld and arr a y is connected ev er y clkin change will po w er up the pld when t urbo bit is off 1 = clkin input to pld and arr a y is disconnected bit 5 0 = clkin input to the pld micro ? cells is connected 1 = clkin input to the pld micro ? cells is disconnected bit 6 0 = super visor y cloc k input to the gpld is connected 1 = super visor y cloc k input to the gpld is disconnected bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 * super v pld pld * cmiser apd ale pd clk mcell clk arr a y clk enab le p olar ity 1 = off 1 = off 1 = off 1 = on 1 = on 1 = high t able 33. power management mode registers (pmmr0, pmmr1)** pmmr0 * * bits 3 and 7 are not used, and should set to 0. ** both the pmmr0 and pmmr1 register bits are clear to z ero f ollo wing po w er up . subsequent reset pulses will not clear the registers . bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 * * * * * * sleep apd mode clk enab le source 1 = on 1= clkin pmmr1 bit 0 0 = super visor y cloc k ser v es as apd cloc k 1 = clkin ser v es as the apd cloc k bit 1 0 = sleep mode is disab led 1 = sleep mode is enab led * un used bits should be set to 0. apd ale enable bit pd polarity ale level apd counter 0 x x not counting 1 x pulsing not counting 1 1 1 counting (gener ates pdn after 15 cloc ks) 1 0 0 counting (gener ates pdn after 15 cloc ks) t able 34. apd counter operation power management unit (cont.)
psd7xx family 13-64 power management unit (cont.) other power saving options the psd7xx off ers other reduced po w er sa ving options that are independent of the p o w er do wn or sleep mode . except f or the sram standb y and csi input f eatures , the y are enab led b y setting bits in the pmmr 0 register . o cmiser bit the cmiser bit resides in pmmr0. this bit controls the a c po w er consumption and access time of the epr om and sram. when in 8 bit data b us mode and cmiser is set, the psd7xx will consume the lo w est le v el of a c po w er . ho w e v er , the access time will be slo w er (see cmiser adder in timing par ameters). when cmiser bit is off , the a c po w er is higher and the psd7xx will retur n to standard access time . o sram standby mode the sram has a vstb y pin (pc2) that can be connected to a batter y . when v cc becomes lo w er than vstb y then the psd7xx will automatically connect the vstb y as a po w er source to the sram. the sram standb y current ( i stb y) is typically 0.5 a. sram data retention v oltage is 2v minim um. o the csi input pin pd2 of p or t d can be configured in psdsoft as the csi input . when lo w , the signal selects and enab les the inter nal epr om and sram f or read or wr ite oper ations . a high on the csi pin will disab le the epr om and sram and reduce the psd po w er consumption. ho w e v er , the pld remains oper ational when csi is high. o input clock the psd7xx pro vides the option to tur n off the clkin and the super visor y cloc k input to the pld to sa v e a c po w er consumption. the clkin is an input to the pld and arr a y and the output micro ? cells . dur ing po w er do wn or if an y of the clkin input is not being used as par t of the pld logic equation, the cloc k should be disab led to sa v e a c po w er . the clkin will be disconnected from the pld and arr a y or the micro ? cells b y setting bit 4 or 5 to ??in the pmmr0.
psd7xx family 13-65 super visor y function the super visor y function in the psd7xx significantly impro v es microcontroller system reliability with prog r ammab le f eatures such as po w er supply monitor ing, reset control and w atchdog timer . these f eatures are: o 5% and 10% po w er supply monitor ing o reset gener ation based on v ar ious conditions: p o w er-on reset; v oltage compar ator with prog r ammab le inter nal or e xter nal tr ip point push button or system reset input w atchdog timer output o user prog r ammab le w atchdog timer (controlled b y ppld product ter ms). o batter y-bac kup of inter nal sram. o wr ite protect of inter nal sram and e xter nal memor y . o reset input debouncer filter . o prog r ammab le reset pulse width gener ator figure 31 is the b loc k diag r am of the super visor y function. the input and output super visor y pins are listed in t ab le 35. pins that are not used can be configured f or other psd7xx i/o functions . t ab le 36 sho ws the inputs and outputs of the ppld that are in v olv ed in controlling the super visor y function. input pin output pin pin name description pin name description vstby (pc2) sram batter y bac kup vstby on (pc4) pin is dr iv en high input when psd7xx is s witched o v er to standb y v oltage vtrip (pc6) exter nal t r ip v oltage ceout (pc3) chip select output input f or the v oltage that can be used f or compar ator e xter nal non-v olatile wr itab le memor y . this chip select becomes inactiv e automatically when the psd7xx is s witched to standb y v oltage . use to conser v e po w er in e xter nal batter y bac kup sram or pre v ent unw anted wr ites to e xter nal eepr om, sram, or flash. reset system or push b utton rst_out (pc5) activ e high reset reset input output clkin (pd1) exter nal cloc k input rst_out (pc1) activ e lo w reset output t able 35. super visor y i/o pins
psd7xx family 13-66 input signals description output signals description greset reset gener ated b y the wdog_en a product ter m that w atchdog timer , enab les the w atchdog or v oltage compar ator or timer . an activ e high reset pin input. pulse of minim um 20ns dur ation. ereset ereset is the output of the pulse gener ator that is tr iggered b y greset . greset or ereset is an activ e lo w signal. wdog_on activ e high w atchdog wdog_clr a product ter m that output. will remain clears and re-loads activ e until the the w atchdog timer . w atchdog is cleared an activ e high pulse b y wdog_clr. of minim um 20ns dur ation. gpld inputs other gpld inputs , ref er to the gpld chapter . super v_clk the cloc k gener ated b y the super visor y function. if the w atchdog timer r uns on the inter nal oscillator , super v_clk is connected to the 2khz oscillator . otherwise super v_clk is connected to the e xter nal clkin/8192. t able 36. ppld super visor y i/o signals super visor y function (cont.)
psd7xx family 13-67 vstby pc4 pc3 pc1 v cc in v cc vstbyon vstbyon int vtp select m u x m u x m u x m u x + ceout rst out rst out (gpld) mcellc3 ceout control programmable pulse genera t or greset ereset mux wdog on greset or ereset wdog clr wdog en en wdog ppld pld inputs super v clk clkin pd1 ext clk clock divisor deb clk debouncer embedded osc 2khz st a tus register clk wdog rst en ld programable w a tchdog timer wdog clk digit al sampler 32khz osc 1.29v bandgap ref ext .vtp reset pc6 pc5 pc2 + m rst vtp rst v cc out t o on-chip sram (onl y) super visor y function (cont.) figur e 31. super visor y function block diagram
psd7xx family 13-68 reset generation the psd7xx can gener ate output reset signals that go out to the e xter nal per ipher als and the microcontroller . three sources are capab le of issuing reset: o p o w er-on reset; v oltage compar ator with prog r ammab le inter nal or e xter nal tr ip point. o push b utton or system reset input from the rst pin. o w atchdog timer timeout output when enab led the microcontroller can read the psd7xx status register to deter mine the source of the reset. the inter nal global reset (greset) can be brought out to pins on p or t c as an activ e lo w or high output. the width of the e xtended reset output (ereset) pulse is user configur ab le and is controlled b y the prog r ammab le pulse gener ator . either greset or ereset (activ e high) can be declared as an inter nal node in psdabel and par ticipate in the logic equation definition. push button reset input the psd7xx has a dedicated activ e-lo w reset input pin that can be connected to a system reset or a push b utton reset. the system reset is a direct input to the reset gener ator , while the push button input is routed through a selectab le debouncer filter that filters out tr ansitions shor ter than three cloc k cycles . the cloc k source of this debouncer is either a 125hz inter nal oscillator or clkin/128k. figure 46 sho ws the reset pin input timing requirement. the activ e lo w r ange has a minim um tnlnh dur ation. after the r ising edge of reset, the psd7xx remains in the reset state dur ing topr r ange . t ab le 37 sho ws the i/o pin status of the psd7xx dur ing the reset and po w er do wn mode . super visor y function (cont.) por t configuration reset power down mode mcu i/o input unchanged pld output activ e depends on inputs to the pld address out t r i-stated not defined data p or t t r i-stated t r i-stated p er ipher al i/o t r i-stated t r i-stated t able 37. status during reset and power down mode register reset power down mode pmmr0 & 1 cleared (po w er up reset) unchanged unchanged (w ar m reset) micro ? cell flip-flop unchanged * unchanged * all other registers cleared to ? unchanged * the micro ? cell flip-flop can be cleared or set b y the reset input or the pdn (p o w er do wn) signal, depending on the .re and .pr equations that are defined in the psdabel file .
psd7xx family 13-69 the power monitor the p o w er monitor circuitr y monitors the v cc supply and gener ates a reset pulse whene v er v cc drops belo w the selected ref erence v oltage . the v oltage compar ator compares v cc either with an inter nally gener ated ref erence v oltage or with an e xter nal ref erence v oltage applied at the v t p (pc6) pin. the v oltage compar ator output can be applied directly to the reset gener ator or go through a 100-microsecond digital sampler . the digital sampler acts as a filter to eliminate an y f alse tr ips that are created b y v cc noises . the digital sampler r uns on an inter nal 32khz oscillator , masking out an y v oltage compar ator output that is less than 3 oscillator cloc k cycles in dur ation. if the e xter nal v oltage ref erence is selected, an e xter nal resistor v oltage divider is used to pro vide the desired v oltage input le v el that is compared with the inter nal bandgap ref erence v oltage of 1.29v . the v oltage divider is sho wn in figure 32 where vmon is connected to the monitored v cc supply . a typical application w ould be r2 is 10k ohm and vmon is 4.75v . the v alue of r1 is calculated as f ollo ws: v t p = vmon x (r2 /( r1 + r2 ) ) r1 = (4.75v x 10k ) /1.29v - 10k = 26.8k an inter nal reset is gener ated when vmon drops belo w 4.75v . super visor y function (cont.) pc1 pc2 pc3 pc4 pc5 pc6 rst out vstby ceout vstbyon rst out vtp psd7xx v mon r1 r2 figur e 32. v oltage divider cir cuit for v t p
psd7xx family 13-70 super visor y function (cont.) the power monitor (cont.) the configur ation options of the v oltage compar ator pro vided in the psdsoft design t ool are: o ref erence v oltage source o inter nal ref erence v oltage le v el o digital sampler o v oltage compar ator disab le the inter nal v t p le v el selections are sho wn in t ab le 38. t w o v cc po w er supply options are a v ailab le: v cc 5% or v cc 10%. depending on the selected v cc po w er supply option, a fix ed v t p v alue is pro vided. vtp range device v cc power min. t ypical max. psd7xxs5 5v 5% 4.47 4.61 4.75 5v 10% 4.08 4.29 4.50 t able 38. inter nal vtp selection pr ogrammable w atchdog t imer the w atchdog timer consists of a retr igger ab le 9 bit counter . once enab led, it star ts counting do wn from an initial v alue that is specified b y the user in the psdsoft design t ool. a w atchdog timeout is gener ated when the count reaches z ero . the timeout output is connected to the ppld and the inter nal reset pulse gener ator . the w atchdog timer is enab led and controlled b y the inter nal reset and the ppld outputs: o inter nal reset the w atchdog timer star ts to count immediately after the tr ailing edge on the e xtended reset (ereset) pulse if it is enab led in the psdsoft design tool. o ppld outputs wdog_en ? if the wdog_en signal is defined in psdabel, the w atchdog timer star ts counting only after wdog_en gener ates a high pulse . this signal can be defined in ter ms of the microcontroller address and the wr ite signal. wr iting to this address b y the microcontroller will enab le the w atchdog timer . the wdog_en signals can be activ ated only after the e xtended reset (ereset) e xpires . wdog_clr ? this ppld output signal re-loads and re-tr iggers the w atchdog timer . this signal is used to clear the w atchdog bef ore a timeout is reached, and can be defined in ter ms of the microcontroller address and the wr ite signal. wr iting to this address b y the microcontroller will clear the w atchdog.
psd7xx family 13-71 w atchdog t imeout output once enab led, the w atchdog timer counts do wn using the selected cloc k r ate . it is re-loaded b y the ppld output wdog_clr or inter nal reset. if the w atchdog is not re-loaded in the time per iod specified in the psdsoft design t ool, the w atchdog times out and gener ates the wdog_rst signal to the reset gener ator and wdog_on to the ppld . the wdog_on signal can be used as a gpld output to gener ate an interr upt to the microcontroller . the wdog_rst signal can create an inter nal reset pulse and activ ate the rst_out pins . the pulse width of the rst_out and wdog_on output is controlled b y the pulse gener ator . w atchdog t imer in power -down mode when the psd7xx enters into po w er do wn mode , the w atchdog timer contin ues to count and the oper ation is not aff ected. the rst_out and ppld are still fully functional. the psd7xx consumes consider ab ly less po w er in the po w er-do wn mode if the inter nal oscillator is selected as the w atchdog cloc k source instead of clkin. batter y backup the pc2 (vstby) pin is the input f or an e xter nal batter y bac kup v oltage f or the onboard sram. as v cc f alls belo w the v alue of vstby , an automatic inter nal po w er s witcho v er occurs which connects the e xter nal batter y po w er to the onboard sram. the minim um sram data retention v oltage is 2.0v and the standb y current is typically 0.5 a. at s witcho v er , the pc3 (ceout) chip select pin is automatically f orced inactiv e and the pc4 (vstby on) pin is dr iv en activ e . ceout can be defined in psdsoft as a chip select f or an e xter nal batter y bac kup sram, flash, or eepr om. dur ing nor mal oper ation, ceout is dr iv en directly b y the output of a micro ? cell (mcell3) to select or deselect the memor y de vice . in batter y bac kup mode , ceout is dr iv en high automatically to deselect the memor y de vice . this ensures minimal po w er consumption (e xter nal batter y bac kup sram) and protects against inadv er tent wr ites dur ing standb y mode . vstby on is an e xter nal indication that the psd has s witched to standb y po w er mode . it can be used at the designer s discretion. super visor y function (cont.)
psd7xx family 13-72 reset debouncer clock sour ce clock w atchdog t imer clock pulse generator clock t imeout pulse w idth fr equency fr equency periods fr equency (ms) inter nal 2khz/16 2khz or f rom 0.5ms 2khz/2 8,16,32,64, oscillator 2khz/256 to 63.875s 128,256,512 2khz (0.5ms increment) exter nal clkin/128k clkin/8k depends on clkin/16k depends on cloc k clkin or clkin clkin clkin/2m f requency f requency t able 39. clock sour ces clock sour ce and fr equency selection with the e xception of the digital sampler which has a dedicated 32khz inter nal oscillator , all other super visor y circuitr y can r un on either the 2khz inter nal oscillator or the e xter nal clkin input. t ab le 39 sho ws the a v ailab le cloc k sources and cloc k inputs to the diff erent circuitr y . based on the selected cloc k source , the psdsoft design t ool pro vides the user with prog r ammab le w atchdog timeout per iods and reset pulse widths . psd7xx reset reset rst out pc1 vstby pc2 ceout pc3 vstby on pc4 rst out pc5 v tp pc6 non-volatile writable memory (battery backed sram, flash, eeprom, etc.) ce typical microcontroller battery for sram backup v cc v cc n.o. momentary 26.8k 10k reset signal is active for watchdog timeout, or v cc drop, or pushbutton activation. * * v = 1.29v when v cc = 4.75v figur e 33. super visor y functions super visor y function (cont.) the figure abo v e sho ws optional usage of the super visor y functions . these f eatures are included in this diag r am: reset input debounce , e xter nal tr ip v oltage configur ation, e xter nal non v olatile wr itab le memor y , and e xter nal standb y po w er source .
psd7xx family 13-73 status register the psd7xx is ab le to gener ate a reset to the microcontroller from three diff erent sources: the w atchdog timer , the v oltage compar ator and the push button reset input. in order to deter mine which source causes the reset, the microcontroller needs to read the status register . after the source of reset is identified, the microcontroller wr ites to the reset_clr register to clear the reset bits in the status register . super visor y function (cont.) status register address :csiop + d8h :csiop + d9h (motorola 16 bit) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 na v e xt_en vtp2 vtp1 vtp0 wdog rst_in vtp rst rst rst t able 40 bit definitions: vtp rst 0 = v cc is abo v e vtp 1 = a reset pulse w as gener ated when v cc le v el had dropped belo w v t p . rst_in 0 = rstin pin is dr iv en high. 1 = a reset pulse w as gener ated when rstin pin had been dr iv en lo w . wdog rst 0 = no w atchdog reset occurred. 1 = a reset pulse w as gener ated when the w atchdog timer e xpired vtp < 2: 0 > : indicates the selected inter nal threshold v oltage ref erence le v el. a v t p reset is issued when v er v cc sta ys belo w the selected ref erence le v el. 0,0,0 ?vtpref = 4.61v 0,0,1 ?vtpref = 2.57v 0,1,0 ?vtpref = 2.76v 0,1,1 ?vtpref = 2.83v 1,0,0 ?vtpref = 3.03v 1,0,1 ?vtpref = not used 1,1,0 ?vtpref = 4.29v 1,1,1 ?vtpref = 0, no tr ip point. v e xt_en: 0 select an inter nal vtp ref erence le v el from the abo v e tab le . 1 enab le pc6 pin to ser v e as an e xter nal v t p input pin. a v t p reset is issued whene v er v cc sta ys belo w pc6 ref erence v oltage le v el. reset_clr register address :csiop + d6h :csiop + d7h (motorola 16 bit) wr iting 00h to this register clears the reset bits in the status register .
psd7xx family 13-74 super visor y function (cont.) super visor y diagnostic registers the super visor y function has f our read-only registers that pro vide additional super visor y and w atchdog timer status f or deb ugging pur poses . the contents of the registers are descr ibed in the f ollo wing tab les . bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 cen_resf ceout stby vstby_on cresb <1> cresb <0> rst_en deb_en sup-pins (r ead only) deb_en 0 = rstin pin has no input filter. 1 = rstin pin is using a debounce filter. rst_en 0 = pc5 pin serves as an active-high reset output. 1 = pc5 pin doesnt serve as an active-high reset output. cresb<1:0> 0,0 = pc1 pin serves as an active-low, cmos reset output. 0,1 = pc1 pin serves as an active-low, open-drain reset output. 1,0 = pc1 pin doesnt serve as an active-low reset output. 1,1 = reserved vstby_on 0 = pc4 pin serves as a battery backup mode indicator (high when vstby > vcc). 1 = pc4 is not used as a battery backup indicator. vs t by 0 = pc2 pin serves as a battery backup input. 1 = pc2 is not used as a battery backup input. ceout 0 = pc3 pin serves as an external memory select, backed-up by the battery input. 1 = pc3 is not used as a battery-backed, external memory select. cen_resf 0 = bypass the vtp reset digital sampler. 1 = v t p reset is using the digital sampler.
psd7xx family 13-75 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 * rst_on crst2pld wdog_ en_ wdog on wd2_ wpt_ enab le wdc k res pwr wdrst_stat (r ead only) super visor y function (cont.) wpt_pwr 0 = watchdog is enabled by the en_wdog pt only. 1 = the watchdog starts counting following reset. wd2_res 0 = watchdog cant issue a reset pulse. 1 = watchdog issues a reset pulse upon completion of its count. wdog_on 0 = watchdog count hasnt expired. 1 = watchdog count has expired. en_wdck 0 = watchdog counter is disabled. 1 = watchdog counter is enabled. wdog_enable 0 = en_wdog pt hasnt been activated yet. 1 = en_wdog pt has already been activated, watchdog is enabled. crs t 2pld 0 = the greset serves as the reset input of the gpld. 1 = the ereset serves as the reset input of the gpld. rst_on 0 = reset is not active. 1 = the extended reset pulse is on.
psd7xx family 13-76 super visor y function (cont.) wdtmo<8:0> current watchdog count. must be read twice. only when two successive reads fetch identical count-values, the count is correct. w d tmo<8> is the most significant bit, w d tmo<0> is the least significant bit. wclk_src<1:0> determines the watchdog clock source. 0,0 = embedded 2khz oscillator. 0,1 = embedded 8hz oscillator. 1,0 = clkin frequency / 8192 (= cl k in / 8k). 1,1 = clkin frequency / 2,097,152 (cl k in / 2m). wd_rst<2:0> defines the watchdog pulse length or reset pulse extension. with wclk_src<1> = 0: 0,0,0 = 8 ms 0,0,1 = 16 ms 0,1,0 = 32 ms 0,1,1 = 64 ms 1,0,0 = 128 ms 1,0,1 = 256 ms 1,1,0 = 512 ms 1,1,1 = 1024 ms ( ~ 1sec) with wclk_src<1> = 1: 0,0,0 = { 8 x [16384 /clki n (h z ) ] } sec 0,0,1 = { 16 x [16384 /clki n (h z ) ] } sec 0,1,0 = { 32 x [16384 /clki n (h z ) ] } sec 0,1,1 = { 64 x [16384 /clki n (h z ) ] } sec 1,0,0 = { 128 x [16384 /clki n (h z ) ] } sec 1,0,1 = { 256 x [16384 /clki n (h z ) ] } sec 1,1,0 = { 512 x [16384 /clki n (h z ) ] } sec 1,1,1 = { 1024 x [16384 /clki n (h z ) ] } sec bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 wdtmo<7> wdtmo<6> wdtmo<5> wdtmo<4> wdtmo<3> wdtmo<2> wdtmo<1> wdtmo<0> wd-timeout1 (r ead only) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 wd_rst<2> wd_rst<1> wd_rst<0> * w c lk_ w c lk_ * wdtmo<8> src<1> src< 0 > wdrst -v ar (r ead only) no te: the super visor y functions ha v e no control/configur ation registers that are accessib le dur ing r un-time . all super visor y function control/configur ation is done using psdsoft.
psd7xx family 13-77 symbol parameter condition min max unit t stg stor age t emper ature cldcc ?65 + 150 c pldcc ?65 + 125 c oper ating t emper ature commercial 0 + 70 c industr ial ?40 + 85 c v oltage on an y pin with respect to gnd ?0.6 + 7 v v pp prog r amming supply v oltage with respect to gnd ?0.6 + 14 v v cc supply v oltage with respect to gnd ?0.6 + 7 v esd protection > 2000 v absolute maximum rating s no te: stresses abo v e those listed under absolute maxim um ratings ma y cause per manent damage to the de vice . this is a stress r ating only and functional oper ation of the de vice at these or an y other conditions abo v e those indicated in the oper ational sections of this specification is not implied. exposure to absolute maxim um rating conditions f or e xtended per iods of time ma y aff ect de vice reliability . range t emperatur e v c c v c c t olerance -70 -90 -15 commercial 0 c to +70 c + 5 v 10% 10% industr ial 40 c to +85 c + 5 v 10% 10% symbol parameter condition min t yp max unit v cc supply v oltage all speeds 4.5 5 5.5 v operating range recommended operating conditions
psd7xx family 13-78 ac/dc parameters the f ollo wing tab les descr ibe the ad/dc par ameters of the psd7xx f amily: o dc electr ical specification o a c timing specification pld timing combinator ial timing synchronous cloc k mode asynchronous cloc k mode input micro ? cell timing microcontroller timing read timing wr ite timing p er ipher al mode timing p o w er do wn and reset timing f ollo wing are some issues concer ning the par ameters presented: o in the dc specification the supply current is giv en f or diff erent modes of oper ation. bef ore calculating the total po w er consumption, deter mine the percentage of time that the psd7xx is in each mode . also the supply po w er is consider ab ly diff erent if the epr om_cmiser is "on". o the a c po w er component giv es the pld , epr om, and sram ma/mhz specification. o in the mcu timing specification add the required time dela y when epr om_cmiser is "on".
psd7xx family 13-79 symbol parameter conditions min typ max unit v cc supply voltage all speeds 4.5 5 5.5 v v ih high level input voltage 4.5 v < v cc < 5.5 v 2 v cc +.5 v v il low level input voltage 4.5 v < v cc < 5.5 v 0.5 0.8 v v ih1 reset high level input voltage (note 1) .8 v cc v cc +.5 v v ih2 v tp pin v cc +.5 v v il1 reset low level input voltage (note 1) ?5 .2 v cc ?1 v v hys reset pin hysteresis 0.3 v 5% v cc = 5v, v tp (2:0) = 0 4.47 4.61 4.75 v v tp power supply trip point 10% v cc = 5v, v tp (2:0) = 6 4.08 4.29 4.50 v v tp (2:0) = 7, no power on reset 0v v etp external trip point (pc6) 1.23 1.29 1.35 v v ol output low voltage i ol = 20 ?, v cc = 4.5 v 0.01 0.1 v i ol = 8 ma, v cc = 4.5 v 0.15 0.45 v v oh output high voltage i oh = 20 ?, v cc = 4.5 v 4.4 4.49 v except vstbyon, ceout i oh = 2 ma, v cc = 4.5 v 2.4 3.9 v v oh1 output high voltage vstbyon, ceout i oh1 = 1 ? v sby ?.5 v sby sram standby voltage 2.0 v cc v i sby sram standby current v cc = 0 v 0.5 1 a i idle idle current (v stby pin) v cc > v sby 0.1 0.1 ? v df sram data retention voltage only on v stby 2v i sb standby supply power down mode csi >v cc ?3 v (note 2) 50 100 ? current sleep mode csi >v cc ?3 v (note 3) 25 50 ? i li input leakage current v ss < v in > v cc ? ?1 1 ? i lo output leakage current .45 < v in > v cc ?0 5 10 ? pld only f = 0 mhz 400 700 ?/pt cmiser = on 00 ma and not selected cmiser = on and eprom eprom adder selected (x8 data bus) 10 15 ma i cc (dc) operating cmiser = on and eprom 15 20 ma (note 4) supply current selected (x16 data bus) cmiser = off 15 20 ma sram not selected 0 0 ma cmiser = on, sram sram adder selected (x8 data bus) 25 40 ma cmiser = on, sram selected (x16 data bus) 30 45 ma i cc (ac) pld 2 3 ma/mhz eprom or sram 2 ma/mhz dc characteristics (5 v 10% versions) notes: 1. reset input has hysteresis. v il1 is valid at or below .2v cc ?1. v ih1 is valid at or above .8v cc . 2. csi deselected or internal pd is active. 3. sleep mode bit is set and internal pd is active. 4. i out = 0 ma.
psd7xx family 13-80 psd7xx ac/dc parameters ? gpld and ecspld t iming (5v 10% v ersions) -70 -90 -15 pt slew symbol parameter conditions min max min max min max aloc rate unit t pd1 ecspld input pin to ecspld (notes 1 & 2) 18 20 24 add 3 ns combinator ial output gpld input pin/f eedbac k to gpld t pd2 combinator ial output p or t c (note 2a) 25 28 32 add 2 ns gpld input pin/f eedbac k to gpld t pd3 combinator ial output p or t a or b (note 2a) 27 30 34 ns gpld input to ecspld output t ea enab le (notes 2 & 2a) 23 25 29 add 3 ns gpld input to gpld output enab le (notes 2a & 2b) 26 28 32 ns gpld input to ecspld output disab le (notes 2 & 2a) 23 25 29 add 3 ns t er gpld input to gpld output disab le (notes 2a & 2b) 26 28 32 ns t arp gpld register clear or (notes 2a & 2b) 26 29 33 ns preset dela y t arpw gpld register clear or preset (notes 2a & 2b) 20 25 29 ns pulse width t ard gpld arr a y dela y an y micro ? cell 16 18 22 add 2 ns gpld and ecspld combinatorial t iming (5 v 10%) no tes: 1. ecspld input pins are a(0:15), pgr(0:3), cntl(0:2), pdn. 2. ecspld outputs are p a(0:3), pb(0:3), pd(0:2). 2a. gpld inputs are a(0:15), pgr(0:3), cntl(0:2), p a(0:7), pb(0:7), pc(0:7), pd(0:2), ale, pdn, reset , wdog_on and wclk. 2b . gpld outputs are p a(4:7), pb(4:7), pc(0:7).
psd7xx family 13-81 no te: 2a. gpld inputs are a(0:15), pgr(0:3), cntl(0:2), p a(0:7), pb(0:7), pc(0:7), pd(0:2), ale, pdn, reset, wdog_on, and wclk. 2c. clkin t clcl = t ch + t cl . -70 -90 -15 pt slew symbol parameter conditions min max min max min max aloc rate unit maxim um f requency exter nal 1/( t s + t co ) 30.30 27.03 25.00 mhz f eedbac k maxim um f requency inter nal f max f eedbac k (f cnt ) 1/( t s + t co ?0) 43.48 37.04 31.25 mhz maxim um f requency pipelined data 1/( t ch + t cl ) 50.00 41.67 35.71 mhz t s input setup time (notes 2a) 15 17 20 add 2 ns t h input hold time (notes 2a) 0 0 0 ns t ch cloc k high time cloc k input 10 12 15 ns t cl cloc k lo w time cloc k input 10 12 15 ns t co cloc k to output dela y cloc k input 18 20 22 ns t ard gpld arr a y dela y an y micro ? cell 16 18 22 add2 ns t min minim um cloc k p er iod t ch + t cl 20 24 29 ns gpld micr o ? cell synchr onous clock mode t iming (5 v 10%) psd7xx ac/dc parameters ? gpld and ecspld t iming (5v 10% v ersions)
psd7xx family 13-82 -70 -90 -15 pt slew symbol parameter conditions min max min max min max aloc rate unit maxim um f requency exter nal 1/( t sa + t co a ) 26.32 25.00 21.74 mhz f eedbac k maxim um f requency inter nal f maxa f eedbac k (f cnt a ) 1/( t sa + t co a ?0) 35.71 33.33 27.78 mhz maxim um f requency pipelined data 1/( t ch + t cl ) 41.67 41.67 35.71 mhz t sa input setup time (note 2a) 8 8 12 add 2 ns t ha input hold time (note 2a) 8 8 12 ns t cha cloc k input high time (note 2a) 12 12 15 ns t cla cloc k input lo w time (note 2a) 12 12 15 ns t co a cloc k to output dela y (note 2a) 30 32 37 ns t ard a gpld arr a y dela y an y micro ? cell 16 18 22 add 2 ns t mina minim um cloc k p er iod 1/ f cnt a 28 30 43 ns gpld micr o ? cell asynchr onous clock mode t iming (5 v 10%) psd7xx ac/dc parameters ? gpld and ecspld t iming (5v 10% v ersions) no te: 2a. gpld inputs are a(0:15), pgr(0:3), cntl(0:2), p a(0:7), pb(0:7), pc(0:7), pd(0:2), ale, pdn, reset, wdog_on, and wclk. 2c. clkin t clcl = t ch + t cl .
psd7xx family 13-83 -70 -90 -15 pt symbol parameter conditions min max min max min max aloc unit t is input setup time (note 2d) 0 0 0 ns t ih input hold time (note 2d) 20 22 26 ns t inh nib input high time (note 2d) 12 14 18 ns t inl nib input lo w time (note 2d) 12 14 18 ns t ino nib input to combinator ial dela y (note 2d) 46 51 59 add 2 ns input micr o ? cell t iming (5 v 10%) psd7xx ac/dc parameters ? gpld and ecspld t iming (5v 10% v ersions) no te: 2d. inputs from p or t a, b and c relativ e to register/latch cloc k from the pld . ale latch timings ref er to t a vlx and t lxax .
psd7xx family 13-84 explanation of ac symbols for pld t iming. example: t a v l x ? time from address v alid to ale in v alid. signal letters a address input c ceout output d input data e e input g inter nal wdog_on signal i interr upt input l ale input n reset input or output p p or t signal output q output data r wr, uds , lds , ds , iord , psen inputs s chip select input t r/w input w inter nal pdn signal b vstb y output m output micro ? cell signal behavior t time l logic le v el lo w or ale h logic le v el high v v alid x no longer a v alid logic le v el z float pw pulse width micr ocontr oller inter face ac/dc parameters (5 v 10% v ersions)
psd7xx family 13-85 -70 -90 -15 cmiser symbol parameter conditions min max min max min max on unit t l vlx ale or as pulse width 18 20 28 ns t a vlx address setup time (note 4) 5 6 10 ns t lxax address hold time (note 4) 7 8 11 ns t a vqv address v alid to data v alid (note 4) 70 90 150 add 10 ns t slqv cs v alid to data v alid 80 100 150 add 10 ns rd to data v alid 8/16-bit bus (note 3) 20 32 40 ns t rlqv rd to data v alid 8-bit bus , 8031, 80251 separ ate mode (note 3a) 32 38 45 ns t rhqx rd data hold time (note 3) 0 0 0 ns t rlrh rd pulse width (note 3) 30 32 38 ns t rhqz rd to data high-z (note 3) 22 25 33 ns t ehel e pulse width 30 32 38 ns t theh r/w setup time to enab le 8 10 18 ns t el tl r/w hold time after enab le 0 0 0 ns address input v alid to in 16-bit bus mode (note 5) 20 30 38 ns t a vpv address output dela y in 8-bit bus mode (note 5) 22 32 48 ns read t iming (5 v 10%) micr ocontr oller inter face ac/dc parameters (5 v 10% v ersions) no tes: 3. rd timing has the same timing as ds , lds , uds , psen (in 8031 combined mode) signals . 3a. rd and psen ha v e the same timing f or 8031 separ ate mode . 4. an y input used to select an inter nal psd7xx function. 5. in m ultiple x ed mode latched address gener ated from adio dela y to address output on an y p or t.
psd7xx family 13-86 -70 -90 -15 symbol parameter conditions min max min max min max unit t l vlx ale or as pulse width 18 20 28 ns t a vlx address setup time (note 4) 5 6 10 ns t lxax address hold time (note 4) 7 8 11 ns t a vwl address v alid to leading edge of wr (notes 4 and 6) 18 20 30 ns t sl wl cs v alid to leading edge or wr (note 6) 22 25 35 ns t d vwh wr data setup time (note 6) 12 15 22 t whdx wr data hold time (note 6) 5 5 5 ns t wl wh wr pulse width (note 6) 18 20 28 ns t whax t r ailing edge of wr to address in v alid (note 6) 0 0 0 ns t whpv t r ailing edge of wr to p or t output v alid using i/o p or t data register (note 6) 25 30 38 ns t whmv wr v alid to p or t output v alid using micro ? cell register prese t /clear (notes 6 and 6a) 25 30 38 ns t d vmv data v alid to p or t output v alid using micro ? cell register prese t /clear (notes 6 and 6b) 25 30 38 ns address input v alid to in 16-bit bus mode (note 5) 20 30 38 ns t a vpv address output dela y in 8-bit bus mode (note 5) 22 32 48 ns w rite t iming (5 v 10%) no te: 6. wr timing has the same timing as e, ds , lds , uds , wrl, wrh signals . 6a. assuming data is stab le bef ore activ e wr ite signal. 6b . assuming wr ite is activ e bef ore data becomes v alid. micr ocontr oller inter face ac/dc parameters (5 v 10% v ersions)
psd7xx family 13-87 -70 -90 -15 symbol parameter conditions min max min max min max unit t wlqv (p a) wr to data propagation dela y (note 6) 25 27 35 ns t d vqv (p a) data to p or t a data propagation dela y (note 9) 22 22 26 ns t whqz (p a) wr in v alid to p or t a t r i-state (note 6) 20 25 33 ns por t a peripheral data mode w rite t iming (5 v 10%) micr ocontr oller inter face ac/dc parameters (5 v 10% v ersions) -70 -90 -15 symbol parameter conditions min max min max min max unit t a vqv (p a) address v alid to data v alid (note 7) 45 55 62 ns t slqv (p a) cs v alid to data v alid 55 55 62 ns rd to data v alid (notes 3, 8) 20 32 40 ns t rlqv (p a) rd to data v alid 8031 mode 32 38 45 ns t d vqv (p a) data in to data out v alid 22 22 26 ns t qxrh (p a) rd data hold time (note 3) 0 0 0 ns t rlrh (p a) rd pulse width (note 3) 30 32 38 ns t rhqz (p a) rd to data high-z (note 3) 20 25 33 ns por t a peripheral data mode read t iming (5 v 10%) no tes: 7. an y input used to select p or t a data p er ipher al mode . 8. data is already stab le on p or t a. 9. data stab le on adio pins to data on p or t a.
psd7xx family 13-88 -70 -90 -15 symbol parameter conditions min max min max min max unit t l vd v ale access time from p o w er do wn 100 120 150 ns t l vd v1 ale or csi access time from sleep 120 150 200 ns gpld and fpld propagation t pd4 dela y in sleep mode 600 600 600 ns t pd5 gpld and fpld reco v er y time after sleep mode 250 250 250 ns maxim um dela y from apd using clkin input 15* t clcl ( s) (note 10) s t cl wh enab le to inter nal pdn v alid signal using w atchdog cloc k 15* t wdclk ( s) s power down t iming (5 v 10%) micr ocontr oller inter face ac/dc parameters (5 v 10% v ersions) no tes: 10. tclcl is the clkin cloc k per iod. see figure 38.
psd7xx family 13-89 symbol parameter conditions min t yp max unit t pdgl propagation dela y from gpld input to clear inter nal wdog_on (note 2a) t pd3 ns t wdpw w atchdog clear (clr_wdog) and enab le (en_wdog) pulse width (note 2a) t rlqv ns f osc inter nal oscillator f requency 1.2 2 2.8 khz w atchdog cloc k and wclk signal 2 13 * t clcl s p er iod ? clkin shor t divisor (clkin/8k) w atchdog cloc k and wclk signal 2 21 * t clcl s p er iod ? clkin long divisor (clkin/2m) t wdclk w atchdog cloc k and wclk signal 0.5 ms p er iod ? inter nal osc with no divisor (2khz) w atchdog cloc k and wclk signal 128 ms p er iod ? inter nal osc with divisor (2khz/256) t wdtmo w atchdog timeout p er iod wd_tmo = 0,1,2......2 9 ? wd_tmo * t wdclk ( s) s (note 11) t chgh w atchdog cloc k to inter nal wdog_on 20 1000 ns high dela y inter nal wdon_on activ e time using pulse gener ator cloc k = 2 n+3 * 2 / f osc (khz) ms t ghgl inter nal oscillator n = 0,1,2,3,4,5,6,7 (note 11) inter nal wdon_on activ e time using pulse gener ator cloc k = 2 n+3 * 16384 * t clcl s exter nal cloc k (clkin) n = 0,1,2,3,4,5,6,7 (note 11) w atchdog and inter nal oscillator t iming (5 v 10%) micr ocontr oller inter face ac/dc parameters (5 v 10% v ersions) no tes: 11. ref er to psdsoft repor t on timing p ar ameters t wdtmo , t ghgl and t nvnx .
psd7xx family 13-90 symbol parameter conditions min typ max unit reset input minimum using internal oscillator 48/f osc (khz) ms active low time with t nlnh debouncer enabled using external clock 393.2 * t clcl (s) ms input pin (clkin) reset input minimum active low time with debouncer disabled 150 ns t opr operational psd after reset input inactive 100 ns rst_out, rst_out output active time pulse generator clock = 2 n+3 * 2/f osc (khz) ms using internal oscillator n = 0,1,2,3,4,5,6,7 (note 11) t nvnx rst_out, rst_out output active time pulse generaror clock= 2 n+3 * 16384 * t clcl ms using external clock (clkin) n = 0,1,2,3,4,5,6,7 (note 11) reset to rst_out, rst_out output valid with debouncer enabled 30 ms t nlnv reset to rst_out, rst_out output valid 100 ns with debouncer disabled v cc fall detect to rst_out, rst_out active 40 100 175 s t vxnv with digital samplerr v cc fall detect to rst_out, rst_out active 12s without digital sampler v cc valid to internal reset active 40 100 150 ms t vvnx with digital sampler v cc valid to internal reset active 12ns without digital sampler v cc and reset timing (5 v 10%) microcontroller interface e ac/dc parameters (5 v 10% versions) notes: 11. refer to psdsoft report on timing parameters t wdtmo , t ghgl and t nvnx .
psd7xx family 13-91 symbol parameter conditions min typ max unit from v cc fall detection (v cc tp) to ceout t nvch high with digital sampler load of 1 ? 40 100 175 ? from v cc fall detection (v cc tp) to ceout high without digital sampler load of 1 ? 1 2 ? ceout recovery time after power up detection load of 1 ? 40 100 175 ? t nxcv (v cc > v cc tp) with digital sampler ceout recovery time after power up detection load of 1 ? 1 2 ? (v cc > v cc tp) without digital sampler ceout timing (5 v 10%) symbol parameter conditions min typ max unit t bvbh vstby detection to vstbyon output high 1.5 2 s t bxbl vstby off detection to vstbyon output low 1.5 2 s vstbyon timing (5 v 10%) microcontroller interface ac/dc parameters (5 v 10% versions)
psd7xx family 13-92 figur e 34. read t iming t avlx t lxax * t lvlx t avqv t slqv t rlqv t rhqx trhqz t eltl t ehel t rlrh t theh t avpv address valid address valid data valid data valid address out ale /as a / d (bhe) multiplexed bus address (bhe / siz0) non-multiplexed bus data non-multiplexed bus csi rd (psen, ds) (lds, uds) e r / w * t a vlx and t lxax are not required f or 80c251 in p age mode or 80c51xa in burst mode .
psd7xx family 13-93 figur e 35. w rite t iming t avlx t lxax t lvlx t avwl t slwl t whdx t whax t el tl t ehel t wlmv t wlwh t d vwh t theh t avpv address valid address valid data valid data valid address out t whpv standard mcu i/o out ale / as a / d (bhe) multiplexed bus address (bhe, siz0) non-multiplexed bus data non-multiplexed bus csi wr (wrh, wrl) (lds, uds) (ds) e r / w
psd7xx family 13-94 figur e 37. peripheral i/o w rite t iming figur e 36. peripheral i/o read t iming t qxrh ( pa) t rlqv ( pa) t rlrh ( pa) t dvqv ( pa) t rhqz ( pa) t slqv ( pa) t avqv ( pa) address data valid ale /as a / d bus rd data on port a csi tdvqv (pa) twlqv (pa) twhqz (pa) address data out a / d bus wr port a data out ale /as
psd7xx family 13-95 figur e 38. combinatorial t iming ? pld tpd1 tpd2 tpd3 gpld input external cs output gpld output ecspld input figur e 39. synchr onous clock mode t iming ? pld t ch t cl t clcl t co t h t s clkin input registered output
psd7xx family 13-96 figur e 40. asynchr onous clock mode t iming (pr oduct-t er m clock) figur e 41. input micr o ? cell t iming (pr oduct-t er m clock) tcha tcla tcoa tha tsa clock input registered output t in h t i n l t ino t i h t i s pt clock input output
psd7xx family 13-97 figur e 42. input to output disabl e / enable figur e 43. asynchr onous rese t / pr eset ter tea input input to output enable / disable tarp register output tarpw reset / preset input
psd7xx family 13-98 figur e 44. power up t iming v cc v stby v stby v cctp t bxbl t vvnx t nvnx t nxcv v stby v cc = reset ( internal ) rst out ( pc1 ) rst out ( pc5 ) vstby on ( pc4 ) ce out ( pc3 ) 0 gnd gnd
psd7xx family 13-99 figur e 45. power down t iming v cc v cc = 0 v cctp v stby t bvbh rst out ( pc5 ) vstby on ( pc4 ) ce out ( pc3 ) ce out ( pc3 ) t vxnv t nvch rst out ( pc1 ) a ctive lo w during po wer do wn a ctive high during po wer do wn vstby vstby vstby gnd gnd gnd
psd7xx family 13-100 figur e 46. reset input t iming figur e 47. key to switching w avefor ms t nlnh t nlnv t nvnx t opr reset rst out ( pc5 ) rst out ( pc1 ) waveforms inputs outputs steady input may change from hi to lo may change from lo to hi don't care outputs only steady output will be changing from hi to lo will be changing lo to hi changing, state unknown center line is tri-state
psd7xx family 13-101 symbol paramete r 1 conditions t ypica l 2 max unit c in capacitance (f or input pins only) v in = 0 v 4 6 pf c out capacitance (f or input/output pins) v out = 0 v 8 12 pf c vpp capacitance (f or wr/v pp or r/w/v pp ) v pp = 0 v 18 25 pf no tes: 1. these par ameters are only sampled and are not 100% tested. 2. t ypical v alues are f or t a = 25 c and nominal supply v oltages . t a = 25 c , f = 1 mhz pin capacitanc e figur e 48. ac t esting input/output w avefor m figur e 49. ac t esting load cir cuit erasur e and pr ogramming 3.0v 0v test point 1.5v device under test 2.01 v 195 w c l = 30 pf (including scope and jig capacitance) t o clear all locations of their prog r ammed contents , e xpose the windo w pac kaged de vice to an ultr a-violet light source . a dosage of 30 w second/c m 2 is required. this dosage can be obtained with e xposure to a w a v elength of 2537 ? and intensity of 12000 w/c m 2 f or 40 to 45 min utes . the de vice should be about 1 inch from the source , and all filters should be remo v ed from the uv light source pr ior to er asure . the psd7xx and similar de vices will er ase with light sources ha ving w a v elengths shor ter than 4000 ?. although the er asure times will be m uch longer than with uv sources at 2537 ?, e xposure to fluorescent light and sunlight e v entually er ases the de vice . f or maxim um system reliability , these sources should be a v oided. if used in such an en vironment, the pac kage windo ws should be co v ered b y an opaque substance . upon deliv er y from wsi, or after each er asure , the psd7xx de vice has all bits in the p ad and epr om in the ??or high state . the configur ation bits are in the ??or lo w state . the code , configur ation, and p ad map data are loaded through the procedure of prog r amming inf or mation f or prog r amming the de vice is a v ailab le directly from wsi. please contact y our local sales representativ e .
psd7xx family 13-102 psd7xx pin assignments pin no. pin assignments pin no. pin assignments 52-pin 52-pin pldcc/ 52-pin pldcc/ 52-pin cldcc pldcc/cldcc cldcc pldcc/cldcc 1 gnd 27 p a2 2 pb5 28 p a1 3 pb4 29 p a0 4 pb3 30 ad0 5 pb2 31 ad1 6 pb1 32 ad2 7 pb0 33 ad3 8 pd2 34 ad4 9 pd1 35 ad5 10 pd0 36 ad6 11 pc7 37 ad7 12 pc6 (vtp) 38 v cc 13 pc5 (rst_out) 39 ad8 14 pc4 (vstby on) 40 ad9 15 v cc 41 ad10 16 gnd 42 ad11 17 pc3 (ceout) 43 ad12 18 pc2 (vstby) 44 ad13 19 pc1 (rst_ou t ) 45 ad14 20 pc0 46 ad15 21 p a7 47 cntl0 22 p a6 48 reset 23 p a5 49 cntl2 24 p a4 50 cntl1 25 p a3 51 pb7 26 gnd 52 pb6
psd7xx family 13-103 psd7xx package infor mation 1 pb0 pb1 pb2 pb3 pb4 pb5 gnd pb6 pb7 cntl1 cntl2 reset cntl0 pa7 pa6 pa5 pa4 pa3 gnd pa2 pa1 pa0 ad0 ad1 ad2 ad3 51 50 49 48 47 52 46 45 44 43 42 41 40 39 38 37 36 35 34 8 9 10 11 12 13 14 15 16 17 18 19 20 7 6 5 4 3 2 v cc pd2 pd1 pd0 pc7 pc6 (vtp) pc5 (rst_out) pc4 (vstbyon) gnd pc3 (ceout) pc2 (vstby) pc1 (rst_out) pc0 ad15 ad14 ad13 ad12 ad11 ad10 v cc ad8 ad9 ad7 ad6 ad5 ad4 21 22 23 24 25 26 27 28 29 30 31 32 33 figur e 49. drawing j7 ? 52-pin plastic leaded chip car rier (pldcc) (package t ype j) 46 45 44 43 42 41 40 39 38 37 36 35 34 ad15 ad14 ad13 ad12 ad11 ad10 v cc v cc ad8 ad9 ad7 ad6 ad5 ad4 pd2 pd1 pd0 pc7 pc6 (vtp) pc5 (rst_out) pc4 (vstbyon) gnd pc3 (ceout) pc2 (vstby) pc1 (rst_out) pc0 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 7 6 5 4 3 2 1 52 51 50 49 48 47 pb0 pb1 pb2 pb3 pb4 pb5 gnd pb6 pb7 cntl1 cntl2 reset cntl0 pa7 pa6 pa5 pa4 pa3 gnd pa2 pa1 pa0 ad0 ad1 ad2 ad3 figur e 50. drawing l6 ? 52-pin ceramic leaded chip car rier (cldcc) with w indow (package t ype l)
psd7xx family 13-104 psd7xxs5-70 specification errata value unit t avlx 5 7 nsec t lxax 7 8 nsec t rlqv 20 24 nsec t wlmv 25 30 nsec t wlqv (pa) 25 32 nsec t wlqz (pa) 20 26 nsec t whax 0 18 nsec t arp 26 40 nsec t ha 8 14 nsec t lv dv 100 180 nsec psd7xxs5-90 t avlx 6 7 nsec t wlqv (pa) 27 32 nsec t wlqz (pa) 25 26 nsec t whax 0 18 nsec t arp 29 40 nsec t ha 8 14 nsec t lv dv 120 180 nsec psd7xxs5-15 t whax 0 18 nsec t arp 31 40 nsec t ha 8 14 nsec t lv dv 140 180 nsec psd7xx product errata errata specifications for product shipping in the first half of 1997 are listed below. product fully meeting specification (no errata parameters) is scheduled to ship in q3 1997. contact your wsi representative or check our web page at www.wsipsd.com for updated information. 5.0v 10% only product data sheet revisions changes original psd7xx e (7/97) 10/97 t vxnv , t nvch , and t nxcv on pgs. 90 and 91 corrected from ns to s product revisions

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